SerDes & High-Speed I/O

Section goal

SerDes lane architecture, equalization behavior, link training, and SI-aware debug from digital integration perspective.

How to study this section

1. Start with topic hubs to learn contract and ownership.

2. Use mechanism and reports pages to map symptoms to root causes.

3. Use debug and worked-example pages for war-room practice.

4. Close with checklist and PPA pages before signing any change.

Topics

1. serdes-basics/ — SerDes Basics

2. equalization-overview/ — Equalization Overview

3. link-training/ — Link Training

4. high-speed-si-awareness/ — High-Speed SI Awareness

Related topics

• AMS course hub

AMS deep dive

SerDes closure requires protocol, training, and SI evidence together.

Concept diagram

SERDES FLOW

training -> equalization -> lane margin -> protocol stability

Metric graph

BER VS EQ

BER
 ^
 |  high  low  high
 +-----------------> EQ setting

Reports and artifacts

• lane BER

• training state transitions

• EQ sweep report

• link retry counters

Mini case study

Link looked protocol-clean but lane margin collapsed under thermal sweep.

Debug branches

• Correlate LTSSM and lane metrics

• Check SI margins

• Review firmware timeout assumptions

Senior review question

Ask: what boundary condition proves this topic is actually closed?