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Course contents

  • How to Use This Course
  • AMS Metrics Reference
  • AMS Interface Glossary
  • Reading Path
  • Analog-Digital Boundaries61
  • PLL & DLL Clocking61
  • SerDes & High-Speed I/O61
    • SerDes Basics
    • Equalization Overview
    • Link Training
      • Link Training: Mechanism
      • Link Training: Inputs & Outputs
      • Link Training: Reports & Metrics
      • Link Training: Debug Playbook
      • Link Training: Worked Example
      • Link Training: Pitfalls & Red Flags
      • Link Training: Interview Drills
      • Link Training: Review Checklist
      • Link Training: Theory Deep Dive
      • Link Training: Design Space
      • Link Training: Expanded Case Study
      • Link Training: Step-by-Step Walkthrough
      • Link Training: Comparison Matrix
      • Link Training: Software / Programmer View
      • Link Training: Silicon PPA Impact
    • High-Speed SI Awareness
    • SerDes & High-Speed I/O: Tricky Q&A
  • ADC / DAC Interfaces61
  • Mixed-Signal Integration61
  • Noise & IR at the Boundary61
  • AMS Interface Interview Prep61
  • AMS Interface Cheatsheet
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‹Link Training
  1. Topics
  2. Analog & Mixed-Signal
  3. SerDes & High-Speed I/O
  4. Link Training
  5. Link Training: Interview Drills

AMS Interface · All levels

Link Training: Interview Drills

Interview Drills for Link Training.

On this page

    Interview drills

    Interview Drills for Link Training focuses on training pass rate, time-to-L0, fallback mode frequency. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.

    Diagram
    PROMPT
    You see training pass rate, time-to-L0, fallback mode frequency on Link Training. Walk through root cause and fix.
    
    STRONG ANSWER
    1. Names boundary and mode.
    2. Explains Training protocols establish lane polarity, timing, equalization, and protocol states; digital state machines must synchronize with PHY indications and timeout policies.
    3. Requests training state trace, firmware log, protocol analyzer capture.
    4. Proposes one bounded fix and full regression.
    
    WEAK ANSWER
    Jumps to random tuning or tool commands without proving mechanism and ownership.

    Diagram to draw on whiteboard

    Training state path

    Diagram
    detect -> poll -> config EQ -> align -> active/L0
          ^                                  |
          +------------- retry/fallback -----+

    Root-cause tree to narrate

    Diagram
    ROOT-CAUSE TREE — Link Training
    
    training pass rate, time-to-L0, fallback mode frequency regressed
            |
    same silicon / run tags?
       /            \
     no              yes
     |                |
    env mismatch    boundary contract or
    tag mismatch    true physical issue
     /   \             |
    clk   reset      isolate first failing
    map   sequence   boundary transition

    AMS deep dive

    SerDes closure requires protocol, training, and SI evidence together.

    Concept diagram

    Diagram
    SERDES FLOW
    
    training -> equalization -> lane margin -> protocol stability

    Metric graph

    Diagram
    BER VS EQ
    
    BER
     ^
     |  high  low  high
     +-----------------> EQ setting

    Reports and artifacts

    • lane BER

    • training state transitions

    • EQ sweep report

    • link retry counters

    Mini case study

    Link looked protocol-clean but lane margin collapsed under thermal sweep.

    Debug branches

    • Correlate LTSSM and lane metrics

    • Check SI margins

    • Review firmware timeout assumptions

    Senior review question

    Ask: what boundary condition proves this topic is actually closed?

    Key takeaways

    • State boundary, mode, and evidence tag with every claim.

    • Always align analog, digital, and physical owners before signoff decisions.

    Common pitfalls

    • Fixing averages while tails still fail.

    • Skipping package/supply evidence in jitter or SerDes issues.

    • Shipping with waivers that lack owner and expiration criteria.

    Principal AMS review addendum

    Training protocols establish lane polarity, timing, equalization, and protocol states; digital state machines must synchronize with PHY indications and timeout policies.

    Metric: training pass rate, time-to-L0, fallback mode frequency

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    See also

    • Link Training: Mechanism
    • Link Training: Inputs & Outputs
    • Link Training: Reports & Metrics