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Course contents

  • How to Use This Course
  • AMS Metrics Reference
  • AMS Interface Glossary
  • Reading Path
  • Analog-Digital Boundaries61
  • PLL & DLL Clocking61
  • SerDes & High-Speed I/O61
    • SerDes Basics
    • Equalization Overview
    • Link Training
      • Link Training: Mechanism
      • Link Training: Inputs & Outputs
      • Link Training: Reports & Metrics
      • Link Training: Debug Playbook
      • Link Training: Worked Example
      • Link Training: Pitfalls & Red Flags
      • Link Training: Interview Drills
      • Link Training: Review Checklist
      • Link Training: Theory Deep Dive
      • Link Training: Design Space
      • Link Training: Expanded Case Study
      • Link Training: Step-by-Step Walkthrough
      • Link Training: Comparison Matrix
      • Link Training: Software / Programmer View
      • Link Training: Silicon PPA Impact
    • High-Speed SI Awareness
    • SerDes & High-Speed I/O: Tricky Q&A
  • ADC / DAC Interfaces61
  • Mixed-Signal Integration61
  • Noise & IR at the Boundary61
  • AMS Interface Interview Prep61
  • AMS Interface Cheatsheet
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‹Link Training
  1. Topics
  2. Analog & Mixed-Signal
  3. SerDes & High-Speed I/O
  4. Link Training
  5. Link Training: Step-by-Step Walkthrough

AMS Interface · All levels

Link Training: Step-by-Step Walkthrough

Step-by-Step Walkthrough for Link Training.

On this page

    Step-by-step analysis walkthrough

    Use this when you own Link Training during an AMS war room.

    1. Capture failing mode and environmental condition.

    2. Pull synchronized waveform, logs, and report artifacts.

    3. Mark first boundary where legal behavior diverges.

    4. Audit reset/clock/power sequence assumptions.

    5. Check physical coupling contributors (floorplan/power/package) where relevant.

    6. Assign single-thread ownership for the first fix.

    7. Propose bounded change and define success criterion.

    8. Run scenario and safety regressions.

    9. Document findings in closure memo.

    10. Update signoff dashboard and waiver state.

    Artifacts to collect

    • training state trace, firmware log, protocol analyzer capture

    • handoff contract

    • firmware/config tag

    • physical signoff snapshot

    • decision memo

    Decision memo template

    Diagram
    AMS DECISION MEMO — Link Training
    mode/condition:
    metric:
    hypothesis:
    fix:
    regression:
    owners: firmware owner, PHY owner, system validation lead

    Reference visuals

    Training state path

    Diagram
    detect -> poll -> config EQ -> align -> active/L0
          ^                                  |
          +------------- retry/fallback -----+

    AMS deep dive

    SerDes closure requires protocol, training, and SI evidence together.

    Concept diagram

    Diagram
    SERDES FLOW
    
    training -> equalization -> lane margin -> protocol stability

    Metric graph

    Diagram
    BER VS EQ
    
    BER
     ^
     |  high  low  high
     +-----------------> EQ setting

    Reports and artifacts

    • lane BER

    • training state transitions

    • EQ sweep report

    • link retry counters

    Mini case study

    Link looked protocol-clean but lane margin collapsed under thermal sweep.

    Debug branches

    • Correlate LTSSM and lane metrics

    • Check SI margins

    • Review firmware timeout assumptions

    Senior review question

    Ask: what boundary condition proves this topic is actually closed?

    Key takeaways

    • State boundary, mode, and evidence tag with every claim.

    • Always align analog, digital, and physical owners before signoff decisions.

    Common pitfalls

    • Fixing averages while tails still fail.

    • Skipping package/supply evidence in jitter or SerDes issues.

    • Shipping with waivers that lack owner and expiration criteria.

    Principal AMS review addendum

    Training protocols establish lane polarity, timing, equalization, and protocol states; digital state machines must synchronize with PHY indications and timeout policies.

    Metric: training pass rate, time-to-L0, fallback mode frequency

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    See also

    • Link Training: Mechanism
    • Link Training: Inputs & Outputs
    • Link Training: Reports & Metrics