High-Speed SI Awareness converts analog-digital assumptions into a measurable engineering contract. At multi-Gbps speeds, package/channel discontinuities and return-path quality convert into jitter and eye closure that appear as digital protocol instability. The hard part is proving which boundary broke first, under which mode, and with which evidence.
When SI-induced retries, lane margin, intermittent link drop rate moves, can you isolate the first failing boundary, identify owner, and define the smallest reversible change that proves root cause?
AMS CLOSURE FLOW — High-Speed SI Awareness
spec + handoff assumptions
|
v
boundary implementation (wrapper/cells/reset)
|
v
physical context (floorplan/power/package)
|
v
metrics + artifacts (jitter/BER/noise/validity)
|
v
root-cause classification -> bounded fix -> regression
Debug rule: always name mode, boundary, evidence tag, and owner.Start every study session by drawing the contract before opening logs or reports. The diagrams below are what to reproduce on whiteboard.
package + board discontinuities -> eye closure/jitter -> retries/link drops
digital symptoms often originate in electrical margin.AMS BOUNDARY SEQUENCE — High-Speed SI Awareness
analog macro -> wrapper / boundary cell -> synchronizer or sampler -> digital consumer
| | | |
analog assumptions legal voltage/state clock/reset contract protocol/data validity
metric under watch: SI-induced retries, lane margin, intermittent link drop rateAMS OWNERSHIP LAYERS — High-Speed SI Awareness
layer owns failure mode
------------------ ---------------------------------- --------------------------
spec contract clocks/resets/interfaces hidden assumption drift
wrapper logic synchronizers/framing/flags silent data corruption
physical integration floorplan/isolation/power coupled noise and droop
signoff governance waivers/checklists/dashboard release with blind spots
closure debug order + regression fix regresses another modePrimary metric: SI-induced retries, lane margin, intermittent link drop rate.
Primary artifact: channel compliance report, lane margin scan, SI waiver sheet.
Owners to bring into review: package owner, SI/PI owner, SerDes integration owner.
One tagged reproduction and one reduced reproducer.
Cross-check from at least two evidence planes: functional and physical/signoff.
OWNERSHIP MAP — High-Speed SI Awareness
artifact owner
---------------------- -----------------------------
integration artifact package owner
implementation artifact SI/PI owner
signoff artifact SerDes integration owner
Every boundary issue needs a named owner before fixes start.Each topic includes mechanism, contract I/O, reports, debug, worked example, pitfalls, interview, checklist, theory, design-space, extended case study, walkthrough, comparison matrix, software view, and silicon PPA impact.
Carry boundary and mode context with every metric.
Prove mechanism with tagged evidence before changing silicon-facing logic.
Close with explicit owner-aligned regression criteria.
Assuming lock/ready/valid means healthy behavior.
Ignoring package and power contributors in jitter/SerDes issues.
Waivers without expiry, owner, or mitigation plan.
SerDes closure requires protocol, training, and SI evidence together.
SERDES FLOW
training -> equalization -> lane margin -> protocol stabilityBER VS EQ
BER
^
| high low high
+-----------------> EQ settinglane BER
training state transitions
EQ sweep report
link retry counters
Link looked protocol-clean but lane margin collapsed under thermal sweep.
Correlate LTSSM and lane metrics
Check SI margins
Review firmware timeout assumptions
Ask: what boundary condition proves this topic is actually closed?
State boundary, mode, and evidence tag with every claim.
Always align analog, digital, and physical owners before signoff decisions.
Fixing averages while tails still fail.
Skipping package/supply evidence in jitter or SerDes issues.
Shipping with waivers that lack owner and expiration criteria.