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Course contents

  • How to Use This Course
  • AMS Metrics Reference
  • AMS Interface Glossary
  • Reading Path
  • Analog-Digital Boundaries61
  • PLL & DLL Clocking61
  • SerDes & High-Speed I/O61
    • SerDes Basics
    • Equalization Overview
    • Link Training
    • High-Speed SI Awareness
      • High-Speed SI Awareness: Mechanism
      • High-Speed SI Awareness: Inputs & Outputs
      • High-Speed SI Awareness: Reports & Metrics
      • High-Speed SI Awareness: Debug Playbook
      • High-Speed SI Awareness: Worked Example
      • High-Speed SI Awareness: Pitfalls & Red Flags
      • High-Speed SI Awareness: Interview Drills
      • High-Speed SI Awareness: Review Checklist
      • High-Speed SI Awareness: Theory Deep Dive
      • High-Speed SI Awareness: Design Space
      • High-Speed SI Awareness: Expanded Case Study
      • High-Speed SI Awareness: Step-by-Step Walkthrough
      • High-Speed SI Awareness: Comparison Matrix
      • High-Speed SI Awareness: Software / Programmer View
      • High-Speed SI Awareness: Silicon PPA Impact
    • SerDes & High-Speed I/O: Tricky Q&A
  • ADC / DAC Interfaces61
  • Mixed-Signal Integration61
  • Noise & IR at the Boundary61
  • AMS Interface Interview Prep61
  • AMS Interface Cheatsheet
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‹High-Speed SI Awareness
  1. Topics
  2. Analog & Mixed-Signal
  3. SerDes & High-Speed I/O
  4. High-Speed SI Awareness
  5. High-Speed SI Awareness: Debug Playbook

AMS Interface · All levels

High-Speed SI Awareness: Debug Playbook

Debug Playbook for High-Speed SI Awareness.

On this page

    Debug playbook

    Debug Playbook for High-Speed SI Awareness focuses on SI-induced retries, lane margin, intermittent link drop rate. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.

    AMS debug is a hunt for first divergence, not downstream symptom management. Most costly delays come from wrong-owner first actions.

    Root-cause tree

    Diagram
    ROOT-CAUSE TREE — High-Speed SI Awareness
    
    SI-induced retries, lane margin, intermittent link drop rate regressed
            |
    same silicon / run tags?
       /            \
     no              yes
     |                |
    env mismatch    boundary contract or
    tag mismatch    true physical issue
     /   \             |
    clk   reset      isolate first failing
    map   sequence   boundary transition
    1. Freeze reproducer: mode, firmware/config, and evidence tags.

    2. Find the first boundary signal that diverges.

    3. Map divergence to contract clause and owner.

    4. Classify failure: contract, sequencing, coupling, package, or tool-view mismatch.

    5. Prove mechanism with one reduced reproducer.

    6. Apply smallest reversible fix and rerun cross-domain regressions.

    Review memo template

    Diagram
    STAFF AMS REVIEW MEMO — SerDes & High-Speed I/O / High-Speed SI Awareness
    
    1. Symptom
       - Watched metric: SI-induced retries, lane margin, intermittent link drop rate
       - Failing mode/condition: <power/clock/temp/workload>
       - Boundary under suspicion: <macro/wrapper/interface/lane/island>
       - Repro setup: <sim/emulation/lab + firmware/config tags>
    
    2. Mechanism hypothesis
       - Primary mechanism: At multi-Gbps speeds, package/channel discontinuities and return-path quality convert into jitter and eye closure that appear as digital protocol instability.
       - Competing hypothesis: <contract gap, sequencing, physical coupling, package, tooling>
       - Missing evidence: <waveform, report, scope/analyzer capture, dashboard snapshot>
    
    3. Proposed action
       - Minimal reversible change: <RTL/config/layout/policy>
       - Expected metric movement: <delta and conditions>
       - Regression risk: timing, noise, power, performance, compatibility
    
    4. Signoff
       - Re-run artifact: channel compliance report, lane margin scan, SI waiver sheet
       - Required owners: package owner, SI/PI owner, SerDes integration owner
       - Final decision: fix, waive with controls, or escalate

    AMS deep dive

    SerDes closure requires protocol, training, and SI evidence together.

    Concept diagram

    Diagram
    SERDES FLOW
    
    training -> equalization -> lane margin -> protocol stability

    Metric graph

    Diagram
    BER VS EQ
    
    BER
     ^
     |  high  low  high
     +-----------------> EQ setting

    Reports and artifacts

    • lane BER

    • training state transitions

    • EQ sweep report

    • link retry counters

    Mini case study

    Link looked protocol-clean but lane margin collapsed under thermal sweep.

    Debug branches

    • Correlate LTSSM and lane metrics

    • Check SI margins

    • Review firmware timeout assumptions

    Senior review question

    Ask: what boundary condition proves this topic is actually closed?

    Key takeaways

    • State boundary, mode, and evidence tag with every claim.

    • Always align analog, digital, and physical owners before signoff decisions.

    Common pitfalls

    • Fixing averages while tails still fail.

    • Skipping package/supply evidence in jitter or SerDes issues.

    • Shipping with waivers that lack owner and expiration criteria.

    Principal AMS review addendum

    At multi-Gbps speeds, package/channel discontinuities and return-path quality convert into jitter and eye closure that appear as digital protocol instability.

    Metric: SI-induced retries, lane margin, intermittent link drop rate

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    See also

    • High-Speed SI Awareness: Mechanism
    • High-Speed SI Awareness: Inputs & Outputs
    • High-Speed SI Awareness: Pitfalls & Red Flags