PLL & DLL Clocking

Section goal

PLL/DLL architecture, jitter budgeting, lock behavior, and digital-side debug for resilient clock integration.

How to study this section

1. Start with topic hubs to learn contract and ownership.

2. Use mechanism and reports pages to map symptoms to root causes.

3. Use debug and worked-example pages for war-room practice.

4. Close with checklist and PPA pages before signing any change.

Topics

1. pll-architecture/ — PLL Architecture

2. jitter-budgeting/ — Jitter Budgeting

3. lock-and-reset-behavior/ — Lock & Reset Behavior

4. pll-debug-digital-lens/ — PLL Debug from a Digital Lens

Related topics

• AMS course hub

AMS deep dive

Clock quality evidence must include jitter and sequencing, not lock status alone.

Concept diagram

CLOCKING FLOW

reference -> PLL/DLL -> distribution -> endpoint margin

Metric graph

JITTER TREND

jitter ps
  ^
  |   o baseline
  |      o stress mode
  |         o failure edge

Reports and artifacts

• jitter budget

• lock/unlock counters

• phase-noise snapshot

• STA uncertainty deltas

Mini case study

False-lock condition released reset early; endpoint logic sampled unstable clock edge patterns.

Debug branches

• Lock qualification policy

• Reset sequencing check

• Package/supply contributors

Senior review question

Ask: what boundary condition proves this topic is actually closed?