Design space exploration

For Jitter Budgeting, closure options trade robustness, schedule, and margin.

Option A — conservative

• Conservative boundary guard: helps high robustness

• Risk: area and schedule cost

• Validate with: first-silicon risk

Option B — balanced

• Balanced integration policy: helps practical closure

• Risk: needs discipline

• Validate with: production ramp

Option C — aggressive

• Aggressive late ECO: helps quick symptom relief

• Risk: cross-domain regressions

• Validate with: deadline crunch

Option D — structural

• Architecture-level reshaping: helps durable fix

• Risk: long lead time

• Validate with: repeat offenders

DESIGN SPACE — Jitter Budgeting
robustness <-> performance <-> schedule
choose by total jitter budget, deterministic/random split, downstream timing margin on product-representative scenarios

Design pitfalls

• Mode coverage too shallow

• Fixing symptom without ownership alignment

Tradeoff curve

BEFORE / AFTER — Jitter Budgeting

health score
  ^
  |                     --- target
  |         o regressed
  |               o before fix
  |                    o after bounded fix
  +--------------------------------------> debug iteration

Prove signal quality, timing margin, and integration safety together.

AMS deep dive

Clock quality evidence must include jitter and sequencing, not lock status alone.

Concept diagram

CLOCKING FLOW

reference -> PLL/DLL -> distribution -> endpoint margin

Metric graph

JITTER TREND

jitter ps
  ^
  |   o baseline
  |      o stress mode
  |         o failure edge

Reports and artifacts

• jitter budget

• lock/unlock counters

• phase-noise snapshot

• STA uncertainty deltas

Mini case study

False-lock condition released reset early; endpoint logic sampled unstable clock edge patterns.

Debug branches

• Lock qualification policy

• Reset sequencing check

• Package/supply contributors

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

System timing margin is consumed by source jitter, transfer jitter, supply noise, and distribution skew; the budget must close from reference clock to endpoint sampler.

Metric: total jitter budget, deterministic/random split, downstream timing margin