Review Checklist for Jitter Budgeting focuses on total jitter budget, deterministic/random split, downstream timing margin. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.
Boundary assumptions are versioned and signed.
Mode matrix (power/clock/reset/stress) is explicit.
Physical context (floorplan/package/power) is included where relevant.
Metric and artifact references are reproducible.
Waivers have owner, expiry, and mitigation.
Owners signed: timing lead, PLL owner, clock tree owner.
OWNERSHIP MAP — Jitter Budgeting
artifact owner
---------------------- -----------------------------
integration artifact timing lead
implementation artifact PLL owner
signoff artifact clock tree owner
Every boundary issue needs a named owner before fixes start.Clock quality evidence must include jitter and sequencing, not lock status alone.
CLOCKING FLOW
reference -> PLL/DLL -> distribution -> endpoint marginJITTER TREND
jitter ps
^
| o baseline
| o stress mode
| o failure edgejitter budget
lock/unlock counters
phase-noise snapshot
STA uncertainty deltas
False-lock condition released reset early; endpoint logic sampled unstable clock edge patterns.
Lock qualification policy
Reset sequencing check
Package/supply contributors
Ask: what boundary condition proves this topic is actually closed?
State boundary, mode, and evidence tag with every claim.
Always align analog, digital, and physical owners before signoff decisions.
Fixing averages while tails still fail.
Skipping package/supply evidence in jitter or SerDes issues.
Shipping with waivers that lack owner and expiration criteria.
System timing margin is consumed by source jitter, transfer jitter, supply noise, and distribution skew; the budget must close from reference clock to endpoint sampler.
Metric: total jitter budget, deterministic/random split, downstream timing margin
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