Jitter Budgeting: Worked Example

Worked example

Worked Example for Jitter Budgeting focuses on total jitter budget, deterministic/random split, downstream timing margin. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.

A stress workload shows total jitter budget, deterministic/random split, downstream timing margin. The first review mistake is broad blame. A better review tracks one boundary transition, validates contract assumptions, and proves the first failing mechanism in Jitter Budgeting.

Sequence under inspection

AMS BOUNDARY SEQUENCE — Jitter Budgeting

analog macro -> wrapper / boundary cell -> synchronizer or sampler -> digital consumer
      |                 |                         |                     |
  analog assumptions    legal voltage/state       clock/reset contract   protocol/data validity

metric under watch: total jitter budget, deterministic/random split, downstream timing margin

Jitter budget stack

TOTAL JITTER BUDGET
  source jitter
  + PLL intrinsic jitter
  + supply/package induced jitter
  + distribution skew/uncertainty
  = endpoint timing margin consumption

1. Capture tagged waveform/log/report set.

2. Mark mode boundary and first failure timestamp.

3. Map to contract and owner.

4. Compare against jitter budget spreadsheet, phase-noise summary, STA uncertainty map.

5. Propose one reversible fix and predefine regression matrix.

Did the fix work?

BEFORE / AFTER — Jitter Budgeting

health score
  ^
  |                     --- target
  |         o regressed
  |               o before fix
  |                    o after bounded fix
  +--------------------------------------> debug iteration

Prove signal quality, timing margin, and integration safety together.

AMS deep dive

Clock quality evidence must include jitter and sequencing, not lock status alone.

Concept diagram

CLOCKING FLOW

reference -> PLL/DLL -> distribution -> endpoint margin

Metric graph

JITTER TREND

jitter ps
  ^
  |   o baseline
  |      o stress mode
  |         o failure edge

Reports and artifacts

• jitter budget

• lock/unlock counters

• phase-noise snapshot

• STA uncertainty deltas

Mini case study

False-lock condition released reset early; endpoint logic sampled unstable clock edge patterns.

Debug branches

• Lock qualification policy

• Reset sequencing check

• Package/supply contributors

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

System timing margin is consumed by source jitter, transfer jitter, supply noise, and distribution skew; the budget must close from reference clock to endpoint sampler.

Metric: total jitter budget, deterministic/random split, downstream timing margin