Jitter Budgeting: Interview Drills

Interview drills

Interview Drills for Jitter Budgeting focuses on total jitter budget, deterministic/random split, downstream timing margin. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.

PROMPT
You see total jitter budget, deterministic/random split, downstream timing margin on Jitter Budgeting. Walk through root cause and fix.

STRONG ANSWER
1. Names boundary and mode.
2. Explains System timing margin is consumed by source jitter, transfer jitter, supply noise, and distribution skew; the budget must close from reference clock to endpoint sampler.
3. Requests jitter budget spreadsheet, phase-noise summary, STA uncertainty map.
4. Proposes one bounded fix and full regression.

WEAK ANSWER
Jumps to random tuning or tool commands without proving mechanism and ownership.

Diagram to draw on whiteboard

Jitter budget stack

TOTAL JITTER BUDGET
  source jitter
  + PLL intrinsic jitter
  + supply/package induced jitter
  + distribution skew/uncertainty
  = endpoint timing margin consumption

Root-cause tree to narrate

ROOT-CAUSE TREE — Jitter Budgeting

total jitter budget, deterministic/random split, downstream timing margin regressed
        |
same silicon / run tags?
   /            \
 no              yes
 |                |
env mismatch    boundary contract or
tag mismatch    true physical issue
 /   \             |
clk   reset      isolate first failing
map   sequence   boundary transition

AMS deep dive

Clock quality evidence must include jitter and sequencing, not lock status alone.

Concept diagram

CLOCKING FLOW

reference -> PLL/DLL -> distribution -> endpoint margin

Metric graph

JITTER TREND

jitter ps
  ^
  |   o baseline
  |      o stress mode
  |         o failure edge

Reports and artifacts

• jitter budget

• lock/unlock counters

• phase-noise snapshot

• STA uncertainty deltas

Mini case study

False-lock condition released reset early; endpoint logic sampled unstable clock edge patterns.

Debug branches

• Lock qualification policy

• Reset sequencing check

• Package/supply contributors

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

System timing margin is consumed by source jitter, transfer jitter, supply noise, and distribution skew; the budget must close from reference clock to endpoint sampler.

Metric: total jitter budget, deterministic/random split, downstream timing margin