Jitter Budgeting converts analog-digital assumptions into a measurable engineering contract. System timing margin is consumed by source jitter, transfer jitter, supply noise, and distribution skew; the budget must close from reference clock to endpoint sampler. The hard part is proving which boundary broke first, under which mode, and with which evidence.
When total jitter budget, deterministic/random split, downstream timing margin moves, can you isolate the first failing boundary, identify owner, and define the smallest reversible change that proves root cause?
AMS CLOSURE FLOW — Jitter Budgeting
spec + handoff assumptions
|
v
boundary implementation (wrapper/cells/reset)
|
v
physical context (floorplan/power/package)
|
v
metrics + artifacts (jitter/BER/noise/validity)
|
v
root-cause classification -> bounded fix -> regression
Debug rule: always name mode, boundary, evidence tag, and owner.Start every study session by drawing the contract before opening logs or reports. The diagrams below are what to reproduce on whiteboard.
TOTAL JITTER BUDGET
source jitter
+ PLL intrinsic jitter
+ supply/package induced jitter
+ distribution skew/uncertainty
= endpoint timing margin consumptionAMS BOUNDARY SEQUENCE — Jitter Budgeting
analog macro -> wrapper / boundary cell -> synchronizer or sampler -> digital consumer
| | | |
analog assumptions legal voltage/state clock/reset contract protocol/data validity
metric under watch: total jitter budget, deterministic/random split, downstream timing marginAMS OWNERSHIP LAYERS — Jitter Budgeting
layer owns failure mode
------------------ ---------------------------------- --------------------------
spec contract clocks/resets/interfaces hidden assumption drift
wrapper logic synchronizers/framing/flags silent data corruption
physical integration floorplan/isolation/power coupled noise and droop
signoff governance waivers/checklists/dashboard release with blind spots
closure debug order + regression fix regresses another modePrimary metric: total jitter budget, deterministic/random split, downstream timing margin.
Primary artifact: jitter budget spreadsheet, phase-noise summary, STA uncertainty map.
Owners to bring into review: timing lead, PLL owner, clock tree owner.
One tagged reproduction and one reduced reproducer.
Cross-check from at least two evidence planes: functional and physical/signoff.
OWNERSHIP MAP — Jitter Budgeting
artifact owner
---------------------- -----------------------------
integration artifact timing lead
implementation artifact PLL owner
signoff artifact clock tree owner
Every boundary issue needs a named owner before fixes start.Each topic includes mechanism, contract I/O, reports, debug, worked example, pitfalls, interview, checklist, theory, design-space, extended case study, walkthrough, comparison matrix, software view, and silicon PPA impact.
Carry boundary and mode context with every metric.
Prove mechanism with tagged evidence before changing silicon-facing logic.
Close with explicit owner-aligned regression criteria.
Assuming lock/ready/valid means healthy behavior.
Ignoring package and power contributors in jitter/SerDes issues.
Waivers without expiry, owner, or mitigation plan.
Clock quality evidence must include jitter and sequencing, not lock status alone.
CLOCKING FLOW
reference -> PLL/DLL -> distribution -> endpoint marginJITTER TREND
jitter ps
^
| o baseline
| o stress mode
| o failure edgejitter budget
lock/unlock counters
phase-noise snapshot
STA uncertainty deltas
False-lock condition released reset early; endpoint logic sampled unstable clock edge patterns.
Lock qualification policy
Reset sequencing check
Package/supply contributors
Ask: what boundary condition proves this topic is actually closed?
State boundary, mode, and evidence tag with every claim.
Always align analog, digital, and physical owners before signoff decisions.
Fixing averages while tails still fail.
Skipping package/supply evidence in jitter or SerDes issues.
Shipping with waivers that lack owner and expiration criteria.