Debug playbook

Debug Playbook for PLL Architecture focuses on lock time, output jitter, frequency accuracy, spur visibility. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.

AMS debug is a hunt for first divergence, not downstream symptom management. Most costly delays come from wrong-owner first actions.

Root-cause tree

ROOT-CAUSE TREE — PLL Architecture

lock time, output jitter, frequency accuracy, spur visibility regressed
        |
same silicon / run tags?
   /            \
 no              yes
 |                |
env mismatch    boundary contract or
tag mismatch    true physical issue
 /   \             |
clk   reset      isolate first failing
map   sequence   boundary transition

1. Freeze reproducer: mode, firmware/config, and evidence tags.

2. Find the first boundary signal that diverges.

3. Map divergence to contract clause and owner.

4. Classify failure: contract, sequencing, coupling, package, or tool-view mismatch.

5. Prove mechanism with one reduced reproducer.

6. Apply smallest reversible fix and rerun cross-domain regressions.

Review memo template

STAFF AMS REVIEW MEMO — PLL & DLL Clocking / PLL Architecture

1. Symptom
   - Watched metric: lock time, output jitter, frequency accuracy, spur visibility
   - Failing mode/condition: <power/clock/temp/workload>
   - Boundary under suspicion: <macro/wrapper/interface/lane/island>
   - Repro setup: <sim/emulation/lab + firmware/config tags>

2. Mechanism hypothesis
   - Primary mechanism: PLL loops align VCO phase/frequency to a reference through charge pump and loop filter dynamics; digital configuration determines operating mode and stability margin.
   - Competing hypothesis: <contract gap, sequencing, physical coupling, package, tooling>
   - Missing evidence: <waveform, report, scope/analyzer capture, dashboard snapshot>

3. Proposed action
   - Minimal reversible change: <RTL/config/layout/policy>
   - Expected metric movement: <delta and conditions>
   - Regression risk: timing, noise, power, performance, compatibility

4. Signoff
   - Re-run artifact: PLL architecture note, loop parameter sheet, lock monitor traces
   - Required owners: PLL designer, clock integration owner, firmware owner
   - Final decision: fix, waive with controls, or escalate

AMS deep dive

Clock quality evidence must include jitter and sequencing, not lock status alone.

Concept diagram

CLOCKING FLOW

reference -> PLL/DLL -> distribution -> endpoint margin

Metric graph

JITTER TREND

jitter ps
  ^
  |   o baseline
  |      o stress mode
  |         o failure edge

Reports and artifacts

• jitter budget

• lock/unlock counters

• phase-noise snapshot

• STA uncertainty deltas

Mini case study

False-lock condition released reset early; endpoint logic sampled unstable clock edge patterns.

Debug branches

• Lock qualification policy

• Reset sequencing check

• Package/supply contributors

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

PLL loops align VCO phase/frequency to a reference through charge pump and loop filter dynamics; digital configuration determines operating mode and stability margin.

Metric: lock time, output jitter, frequency accuracy, spur visibility