Extended case study

Signoff review: lock time, output jitter, frequency accuracy, spur visibility regressed after a change touching PLL Architecture.

Background

Team had prior closure; latest integration run shows instability concentrated in one operating condition.

Symptoms observed

• lock time, output jitter, frequency accuracy, spur visibility degradation

• Cross-team disagreement on root cause

• Directed tests pass but system scenario fails

Investigation timeline

1. Hour 0: freeze data tags, firmware build, and environmental conditions

2. Hour 1: diff boundary assumptions and handoff revisions

3. Hour 2: isolate first failing mode and trigger sequence

4. Hour 3: correlate waveform/log/report evidence

5. Hour 4: classify root cause and ownership

6. Hour 5: apply bounded fix

7. Hour 6: execute full regression and issue signoff memo

Root cause

Root cause tied to PLL Architecture: PLL loops align VCO phase/frequency to a reference through charge pump and loop filter dynamics; digital configuration determines operating mode and stability margin.

Fix and validation

• Bounded RTL/config/layout correction

• Re-run PLL architecture note, loop parameter sheet, lock monitor traces

• Full cross-domain regression matrix

Lessons learned

• Tag everything

• Mechanism before commands

• No signoff without owner agreement

CASE STUDY — PLL Architecture
baseline metric / regressed metric / post-fix metric

Sequence under stress

AMS BOUNDARY SEQUENCE — PLL Architecture

analog macro -> wrapper / boundary cell -> synchronizer or sampler -> digital consumer
      |                 |                         |                     |
  analog assumptions    legal voltage/state       clock/reset contract   protocol/data validity

metric under watch: lock time, output jitter, frequency accuracy, spur visibility

AMS deep dive

Clock quality evidence must include jitter and sequencing, not lock status alone.

Concept diagram

CLOCKING FLOW

reference -> PLL/DLL -> distribution -> endpoint margin

Metric graph

JITTER TREND

jitter ps
  ^
  |   o baseline
  |      o stress mode
  |         o failure edge

Reports and artifacts

• jitter budget

• lock/unlock counters

• phase-noise snapshot

• STA uncertainty deltas

Mini case study

False-lock condition released reset early; endpoint logic sampled unstable clock edge patterns.

Debug branches

• Lock qualification policy

• Reset sequencing check

• Package/supply contributors

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

PLL loops align VCO phase/frequency to a reference through charge pump and loop filter dynamics; digital configuration determines operating mode and stability margin.

Metric: lock time, output jitter, frequency accuracy, spur visibility