Review checklist

Review Checklist for PLL Architecture focuses on lock time, output jitter, frequency accuracy, spur visibility. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.

• Boundary assumptions are versioned and signed.

• Mode matrix (power/clock/reset/stress) is explicit.

• Physical context (floorplan/package/power) is included where relevant.

• Metric and artifact references are reproducible.

• Waivers have owner, expiry, and mitigation.

• Owners signed: PLL designer, clock integration owner, firmware owner.

Sign-off ownership

OWNERSHIP MAP — PLL Architecture

artifact                  owner
----------------------    -----------------------------
integration artifact    PLL designer
implementation artifact clock integration owner
signoff artifact        firmware owner

Every boundary issue needs a named owner before fixes start.

AMS deep dive

Clock quality evidence must include jitter and sequencing, not lock status alone.

Concept diagram

CLOCKING FLOW

reference -> PLL/DLL -> distribution -> endpoint margin

Metric graph

JITTER TREND

jitter ps
  ^
  |   o baseline
  |      o stress mode
  |         o failure edge

Reports and artifacts

• jitter budget

• lock/unlock counters

• phase-noise snapshot

• STA uncertainty deltas

Mini case study

False-lock condition released reset early; endpoint logic sampled unstable clock edge patterns.

Debug branches

• Lock qualification policy

• Reset sequencing check

• Package/supply contributors

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

PLL loops align VCO phase/frequency to a reference through charge pump and loop filter dynamics; digital configuration determines operating mode and stability margin.

Metric: lock time, output jitter, frequency accuracy, spur visibility