High-Speed SI Awareness: Design Space

Design space exploration

For High-Speed SI Awareness, closure options trade robustness, schedule, and margin.

Option A — conservative

• Conservative boundary guard: helps high robustness

• Risk: area and schedule cost

• Validate with: first-silicon risk

Option B — balanced

• Balanced integration policy: helps practical closure

• Risk: needs discipline

• Validate with: production ramp

Option C — aggressive

• Aggressive late ECO: helps quick symptom relief

• Risk: cross-domain regressions

• Validate with: deadline crunch

Option D — structural

• Architecture-level reshaping: helps durable fix

• Risk: long lead time

• Validate with: repeat offenders

DESIGN SPACE — High-Speed SI Awareness
robustness <-> performance <-> schedule
choose by SI-induced retries, lane margin, intermittent link drop rate on product-representative scenarios

Design pitfalls

• Mode coverage too shallow

• Fixing symptom without ownership alignment

Tradeoff curve

BEFORE / AFTER — High-Speed SI Awareness

health score
  ^
  |                     --- target
  |         o regressed
  |               o before fix
  |                    o after bounded fix
  +--------------------------------------> debug iteration

Prove signal quality, timing margin, and integration safety together.

AMS deep dive

SerDes closure requires protocol, training, and SI evidence together.

Concept diagram

SERDES FLOW

training -> equalization -> lane margin -> protocol stability

Metric graph

BER VS EQ

BER
 ^
 |  high  low  high
 +-----------------> EQ setting

Reports and artifacts

• lane BER

• training state transitions

• EQ sweep report

• link retry counters

Mini case study

Link looked protocol-clean but lane margin collapsed under thermal sweep.

Debug branches

• Correlate LTSSM and lane metrics

• Check SI margins

• Review firmware timeout assumptions

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

At multi-Gbps speeds, package/channel discontinuities and return-path quality convert into jitter and eye closure that appear as digital protocol instability.

Metric: SI-induced retries, lane margin, intermittent link drop rate