Inputs & Outputs for Link Training focuses on training pass rate, time-to-L0, fallback mode frequency. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.
Treat these inputs and outputs as signed interface guarantees. Ambiguity here creates the most expensive integration bugs.
INPUTS
- AMS handoff contract and spec revision
- mode definitions (power/clock/reset/traffic)
- wrapper and boundary-cell assumptions
- physical constraints: keepouts, guard, package limits
OUTPUTS
- mode-tagged metric report
- owner-signed debug or closure note
- waiver manifest with expiry and controls
- release recommendationAMS BOUNDARY SEQUENCE — Link Training
analog macro -> wrapper / boundary cell -> synchronizer or sampler -> digital consumer
| | | |
analog assumptions legal voltage/state clock/reset contract protocol/data validity
metric under watch: training pass rate, time-to-L0, fallback mode frequencyOWNERSHIP MAP — Link Training
artifact owner
---------------------- -----------------------------
integration artifact firmware owner
implementation artifact PHY owner
signoff artifact system validation lead
Every boundary issue needs a named owner before fixes start.SerDes closure requires protocol, training, and SI evidence together.
SERDES FLOW
training -> equalization -> lane margin -> protocol stabilityBER VS EQ
BER
^
| high low high
+-----------------> EQ settinglane BER
training state transitions
EQ sweep report
link retry counters
Link looked protocol-clean but lane margin collapsed under thermal sweep.
Correlate LTSSM and lane metrics
Check SI margins
Review firmware timeout assumptions
Ask: what boundary condition proves this topic is actually closed?
State boundary, mode, and evidence tag with every claim.
Always align analog, digital, and physical owners before signoff decisions.
Fixing averages while tails still fail.
Skipping package/supply evidence in jitter or SerDes issues.
Shipping with waivers that lack owner and expiration criteria.
Training protocols establish lane polarity, timing, equalization, and protocol states; digital state machines must synchronize with PHY indications and timeout policies.
Metric: training pass rate, time-to-L0, fallback mode frequency
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