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Course contents

  • How to Use This Course
  • AMS Metrics Reference
  • AMS Interface Glossary
  • Reading Path
  • Analog-Digital Boundaries61
  • PLL & DLL Clocking61
  • SerDes & High-Speed I/O61
    • SerDes Basics
      • SerDes Basics: Mechanism
      • SerDes Basics: Inputs & Outputs
      • SerDes Basics: Reports & Metrics
      • SerDes Basics: Debug Playbook
      • SerDes Basics: Worked Example
      • SerDes Basics: Pitfalls & Red Flags
      • SerDes Basics: Interview Drills
      • SerDes Basics: Review Checklist
      • SerDes Basics: Theory Deep Dive
      • SerDes Basics: Design Space
      • SerDes Basics: Expanded Case Study
      • SerDes Basics: Step-by-Step Walkthrough
      • SerDes Basics: Comparison Matrix
      • SerDes Basics: Software / Programmer View
      • SerDes Basics: Silicon PPA Impact
    • Equalization Overview
    • Link Training
    • High-Speed SI Awareness
    • SerDes & High-Speed I/O: Tricky Q&A
  • ADC / DAC Interfaces61
  • Mixed-Signal Integration61
  • Noise & IR at the Boundary61
  • AMS Interface Interview Prep61
  • AMS Interface Cheatsheet
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‹SerDes Basics
  1. Topics
  2. Analog & Mixed-Signal
  3. SerDes & High-Speed I/O
  4. SerDes Basics
  5. SerDes Basics: Review Checklist

AMS Interface · All levels

SerDes Basics: Review Checklist

Review Checklist for SerDes Basics.

On this page

    Review checklist

    Review Checklist for SerDes Basics focuses on link-up success, lane BER, lane deskew margin, protocol errors. The goal is to connect observed symptom to boundary mechanism, ownership, and signoff risk.

    • Boundary assumptions are versioned and signed.

    • Mode matrix (power/clock/reset/stress) is explicit.

    • Physical context (floorplan/package/power) is included where relevant.

    • Metric and artifact references are reproducible.

    • Waivers have owner, expiry, and mitigation.

    • Owners signed: SerDes architect, digital integration owner, bring-up owner.

    Sign-off ownership

    Diagram
    OWNERSHIP MAP — SerDes Basics
    
    artifact                  owner
    ----------------------    -----------------------------
    integration artifact    SerDes architect
    implementation artifact digital integration owner
    signoff artifact        bring-up owner
    
    Every boundary issue needs a named owner before fixes start.

    AMS deep dive

    SerDes closure requires protocol, training, and SI evidence together.

    Concept diagram

    Diagram
    SERDES FLOW
    
    training -> equalization -> lane margin -> protocol stability

    Metric graph

    Diagram
    BER VS EQ
    
    BER
     ^
     |  high  low  high
     +-----------------> EQ setting

    Reports and artifacts

    • lane BER

    • training state transitions

    • EQ sweep report

    • link retry counters

    Mini case study

    Link looked protocol-clean but lane margin collapsed under thermal sweep.

    Debug branches

    • Correlate LTSSM and lane metrics

    • Check SI margins

    • Review firmware timeout assumptions

    Senior review question

    Ask: what boundary condition proves this topic is actually closed?

    Key takeaways

    • State boundary, mode, and evidence tag with every claim.

    • Always align analog, digital, and physical owners before signoff decisions.

    Common pitfalls

    • Fixing averages while tails still fail.

    • Skipping package/supply evidence in jitter or SerDes issues.

    • Shipping with waivers that lack owner and expiration criteria.

    Principal AMS review addendum

    SerDes converts parallel data to high-speed serial lanes with CDR, encoding, and lane management; system behavior depends on alignment, training, and channel quality.

    Metric: link-up success, lane BER, lane deskew margin, protocol errors

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    See also

    • SerDes Basics: Mechanism
    • SerDes Basics: Inputs & Outputs
    • SerDes Basics: Reports & Metrics