Silicon PPA and closure impact

Channel/package quality directly appears as digital link instability.

Area drivers

• Boundary cells and guards add area

• Routing keepouts can increase utilization pressure

Power drivers

• Added margins cost power

• Jitter/noise mitigation can increase static and dynamic budgets

Timing impact

• Jitter and uncertainty consume timing

• IR/noise shifts practical timing margin

PD consequences

• Keepouts and strap topology alter congestion and CTS paths

• Package constraints affect lane routing

Verification burden

• Need aligned AMS + digital + package evidence

• Waiver discipline is mandatory

PPA — SerDes Basics
area/power/timing/closure-time tradeoff

PPA takeaways

• Mixed-signal fixes are multi-objective

• Signoff is cross-team, not single-report

Design option PPA snapshot

BEFORE / AFTER — SerDes Basics

health score
  ^
  |                     --- target
  |         o regressed
  |               o before fix
  |                    o after bounded fix
  +--------------------------------------> debug iteration

Prove signal quality, timing margin, and integration safety together.

AMS deep dive

SerDes closure requires protocol, training, and SI evidence together.

Concept diagram

SERDES FLOW

training -> equalization -> lane margin -> protocol stability

Metric graph

BER VS EQ

BER
 ^
 |  high  low  high
 +-----------------> EQ setting

Reports and artifacts

• lane BER

• training state transitions

• EQ sweep report

• link retry counters

Mini case study

Link looked protocol-clean but lane margin collapsed under thermal sweep.

Debug branches

• Correlate LTSSM and lane metrics

• Check SI margins

• Review firmware timeout assumptions

Senior review question

Ask: what boundary condition proves this topic is actually closed?

Key takeaways

• State boundary, mode, and evidence tag with every claim.

• Always align analog, digital, and physical owners before signoff decisions.

Common pitfalls

• Fixing averages while tails still fail.

• Skipping package/supply evidence in jitter or SerDes issues.

• Shipping with waivers that lack owner and expiration criteria.

Principal AMS review addendum

SerDes converts parallel data to high-speed serial lanes with CDR, encoding, and lane management; system behavior depends on alignment, training, and channel quality.

Metric: link-up success, lane BER, lane deskew margin, protocol errors