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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
  • Races and Controller Design8
    • Transient States and Races
    • Controller Resources
      • MSHRs and Pending Entries
      • Ack Counting and Late Data
      • Retries, NACKs and Credits
      • A Controller Block Diagram
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
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‹Races and Controller Design
  1. Topics
  2. Cache Coherency
  3. Races and Controller Design
  4. Controller Resources

Part 4 · Races and Controller Design · All levels

Controller Resources

Turn protocol obligations into pending entries, acknowledgement tracking, protected buffers and safe acceptance of work.

  • 4topics
  • 4lessons

Controllers need storage for facts that outlive a message: which operation is pending, which acknowledgements remain, where accepted data is protected, and which completion allows reuse. This topic connects those facts to a small controller architecture.

Lesson

After it you can...

MSHRs and Pending Entries

Separate core miss tracking from home transaction tracking.

Ack Counting and Late Data

Require every completion condition, not whichever one arrives first.

Retries, NACKs and Credits

Distinguish acceptance, rejection and buffer capacity.

A Controller Block Diagram

Place state, data and scheduling responsibilities in named resources.

Read after the race topic. Acknowledgements are collected at H and permissions follow the course model.

Check yourself Does an empty acknowledgement set by itself permit a write grant?

No. The transaction may still lack an authoritative data value, the correct grant state, protected output capacity or a matching identity. Each required condition has to be satisfied.

Related topics

  • Shared course model

  • Prerequisite: race policies

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See also

  • Transient States and Races