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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
    • Read and Write-Permission Flows
    • Forwarding Versus Memory Sourcing
    • Writeback, Eviction and Cleaning
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
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‹Cache Coherency
  1. Topics
  2. Cache Coherency
  3. Transactions

Part 3 · Transactions · All levels

Transactions

Read, write, forward and evict a coherent line while tracking both permission and newest data.

  • 3topics
  • 12lessons

Parts 1 and 2 established the meaning of permissions and states. Here you follow their consequences through complete transactions: a requester can lack data, permission or both, and a response must preserve the newest value as well as revoke conflicting rights. Each example starts from a stated snapshot of C0, C1, H and memory.

Three topics in order: request flows, then where the data comes from, then how a cache releases a line.
Study route through the three topics of this section.

Work through the three topics in that order: Read and Write-Permission Flows, then Forwarding Versus Memory Sourcing, then Writeback, Eviction and Cleaning.

Topic

What it covers

Read and Write-Permission Flows

GetS and GetM from cold, shared and upgrade starting points.

Forwarding Versus Memory Sourcing

When memory may supply data and when a cache must, through H.

Writeback, Eviction and Cleaning

PutS, PutE and PutM with Put-Ack, WB entries and cache maintenance.

Evictions are notified (PutS, PutE, PutM, each waiting for Put-Ack). Silent clean eviction is a variant in the last topic.

Twelve lessons

Lesson

After it you can...

Cold Read Miss

Locate the delivered read grant, not just memory response arrival.

Read of a Shared Line

Add a reader without omitting it from future revocations.

Write Miss and Ownership

Acquire the value and exclusive permission from U or from a shared line.

Upgrade from Shared

Separate retained data from the exclusivity still required.

Who May Supply Data?

Justify source authority from state and pending work.

Dirty Intervention

Track pending dirty responsibility until MSI memory is current.

Three-Hop Versus Four-Hop

Compare logical legs without hiding completion assumptions.

When Memory Is Stale

Distinguish legal backing lag from wrong response data.

Dirty Writeback

Say where a dirty value lives from PutM until Put-Ack frees the WB entry.

Clean Eviction: Silent or Notified

Compare PutS and PutE with silent eviction and its stale sharer bit.

Writeback Buffers

Keep a WB entry until Put-Ack, and stall when none is free.

Cache Maintenance Operations

Define clean, invalidate and clean-and-invalidate by target and completion.

Keep the course model beside the tables. H handles one transaction for X at a time in these examples. Races between transactions come in Part 4.

Common pitfall

An apparently finished permission change can still owe a data delivery or a memory write. Check the WB entry, H's buffer and H's pending entry before declaring the transaction done.

Check yourself If no cache array holds X, must a new request use memory?

No. The newest value may still be in C0's WB entry (C0 in MI^A, waiting for Put-Ack) or, in the early Put-Ack variant, in H's buffer before memory is written. H must not serve memory = 0 meanwhile. If the PutM has reached H, H waits for the memory write. If it has not, H still records exclusive(C0) and forwards the request to C0, which answers from its WB entry.

Related topics

  • Shared model and completion assumptions

  • Prerequisite: States and Protocols

  • Start: request flows

PreviousNext: Read and Write-Permission Flows

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See also

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary