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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
    • Read and Write-Permission Flows
      • Cold Read Miss
      • Read of a Shared Line
      • Write Miss and Ownership
      • Upgrade from Shared
    • Forwarding Versus Memory Sourcing
    • Writeback, Eviction and Cleaning
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
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‹Read and Write-Permission Flows
  1. Topics
  2. Cache Coherency
  3. Transactions
  4. Read and Write-Permission Flows
  5. Read of a Shared Line

Part 3 · Transactions · All levels

Read of a Shared Line

Add a second MSI reader without changing the first reader's permission.

On this page

    Does another reader require an invalidation?

    C0 can already read X and C1 now misses. Read-only permissions are compatible, so a second reader does not need to remove the first. That does not mean H can skip recording C1: a later writer will need to find every reader.

    Start at the end of the cold read in MSI: C0 S / 0, C1 I / -, H S{C0}, memory = 0. No transaction is pending. In settled MSI, S means memory is current, so H reads memory to answer C1.

    C1 reads through H, which reads memory; C0 keeps S throughout and H records both readers after the grant.
    A second MSI reader: two messages and a memory read inside H. C0 stays S throughout.

    Step

    C0 state / value

    C1 state / value

    H directory

    Memory

    Newest data

    Checkpoint

    S / 0

    I / -

    S{C0}

    0

    C0 and memory: 0

    1. GetS at H

    S / 0

    IS^D / -

    S{C0}, pend GetS C1

    0

    C0 and memory: 0

    H reads memory

    S / 0

    IS^D / -

    S{C0}, pend GetS C1

    0

    C0 and memory: 0, Data(0) in flight to C1

    2. Data at C1

    S / 0

    S / 0

    S{C0}, pend GetS C1

    0

    C0, C1 and memory: 0

    (assumed) grant delivered

    S / 0

    S / 0

    S{C0,C1}

    0

    C0, C1 and memory: 0

    There is no Inv in this sequence because nobody is being granted write permission. C0 need not send data just because it has a copy: memory is already current. H adds C1 to the sharer set once the grant is delivered (the assumed row, as the course model allows), so a later GetM will invalidate both readers.

    When memory may not answer

    Two cases change this trace. In MESI, if C0 held E rather than S, H would show exclusive(C0) and must forward the read to C0 (see Who May Supply Data?). In MOESI, an S copy can coexist with an O holder and stale memory, so H must ask the O holder. The dirty-responsibility lesson explains who supplies data then.

    Common pitfall

    Granting S to C1 without adding C1 to the sharer set. A later writer would skip a real reader. Correct data cannot make up for a missing directory entry.

    Interview

    Separate compatibility from tracking: S and S can coexist, but H must still record both copies. Explain why neither invalidation nor dirty intervention appears in this trace.

    Check yourself Would S{C0} still be safe after step 2 if it is meant to list every possible reader?

    No. It would omit C1, an actual reader. A sharer list may contain extra possible holders, but it must never omit a real one, because it decides who gets Inv.

    Related topics

    • Shared course model

    • Next: a writer needs exclusivity

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