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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
    • Whiteboard Frameworks for Coherency
    • Staff-Level Design Reviews
    • Program Risk and Escalation Playbooks
    • Coherency Interview Q&A Bank
  • Capstone: A Coherent Model Lab5
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‹Cache Coherency
  1. Topics
  2. Cache Coherency
  3. Interview and Design Review

Part 13 · Interview and Design Review · All levels

Interview and Design Review

Answer coherence questions with a clear framework, review protocol changes like a senior engineer, manage coherence risk on a chip program, and practise with a graded question bank.

  • 4topics
  • 17lessons

Topics in this section

  1. 1Whiteboard Frameworks for Coherency4 lessons
    • The Answer Framework
    • Drawing a Transaction
    • Explaining a Race
    • Grading Rubric
  2. 2Staff-Level Design Reviews4 lessons
    • Reviewing a Protocol Change
    • Design Review Checklist
    • Writing a Design Memo
    • Trade-Off Questions
  3. 3Program Risk and Escalation Playbooks4 lessons
    • Coherence Risk Register
    • Late Bug Decisions
    • An Escalation Scenario
    • Sign-off Criteria
  4. 4Coherency Interview Q&A Bank5 lessons
    • Fundamentals Q&A
    • Transactions and Races Q&A
    • Ordering Q&A
    • Verification and Debug Q&A
    • Architecture Q&A

Knowing the mechanisms of Parts 1 to 12 is not the same as explaining them under pressure or deciding with them on a real program. This part turns the course into practice: a four-step answer framework (Assumption, Mechanism, Trade-off, Evidence) and a whiteboard routine for drawing a transaction, how a senior engineer reviews a protocol change and writes a design memo, how coherence risk is tracked and escalated before tape-out, and a question bank graded on a 0 to 4 rubric. Nothing here adds new protocol content: every answer links back to the lesson that teaches it.

Learning path through the four Part 13 topics.
Suggested order: the framework first, then use the question bank alongside the review and program topics.

Seventeen lessons

Lesson

After it you can...

The Answer Framework

Structure any coherence answer as assumption, mechanism, trade-off, evidence.

Drawing a Transaction

Draw a correct transaction with its state/value table in minutes.

Explaining a Race

Explain who wins, who waits and why the data stays safe.

Grading Rubric

Grade an answer from 0 to 4.

Reviewing a Protocol Change

Find the new races and costs a protocol change brings.

Design Review Checklist

Run a coherence design review with evidence for each item.

Writing a Design Memo

Write a short memo that a team can decide from.

Trade-Off Questions

Answer senior trade-off questions with the deciding conditions.

Coherence Risk Register

Rank coherence risks on a chip program.

Late Bug Decisions

Choose between a fix, a workaround and an erratum.

An Escalation Scenario

Run a late hang investigation to a decision.

Sign-off Criteria

State the evidence a coherent design needs before tape-out.

Fundamentals Q&A

Answer invariant, state and snoop-versus-directory questions.

Transactions and Races Q&A

Answer transaction, race and controller questions.

Ordering Q&A

Answer memory-model, fence and atomic questions.

Verification and Debug Q&A

Answer checking, formal, coverage and triage questions.

Architecture Q&A

Answer scaling, hierarchy, protocol and integration questions.

Attempt each question on paper before reading its answer, then grade yourself with the rubric. A strong answer always says which model it assumes: the same question has different correct answers under MSI and MOESI, with acks at the home or at the requester, and under TSO or a weak memory model.

Check yourself An interviewer asks: "Why do we need transient states?" What makes the difference between a 2 and a 4 on the rubric?

A 2 explains the mechanism: a request is in flight, so the cache is neither in its old nor its new stable state and must stall or handle certain messages. A 4 also states the assumption (an unordered network, acks collected at the home), names a concrete race the transient state resolves (an Inv arriving in SM^D), gives the trade-off (more states to verify), and says how it would be checked (state-by-event coverage, a model checker). The mechanism alone is not enough for a 4.

Related topics

  • Shared course model

  • Revision sheet

  • Races and controllers

  • Verification

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See also

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary