Because they start in the middle. "The other core gets invalidated" may be true, but without the model it is unfalsifiable, and without a cost or a check it is a definition, not engineering. The course's framework fixes the order of an answer to four parts. Each part has a concrete content list, so you can tell while speaking which part you have not covered yet.
Part | Say concretely | Course lessons it draws on |
|---|---|---|
Assumption | Protocol (MSI, MESI, MOESI), snooping or directory, where the home is, network ordering (none assumed by default), delivery (reliable), who collects Inv-Acks, the starting snapshot. | Course model, Snooping on a Shared Bus, Directory, Home and Sharers |
Mechanism | The stable and transient states each cache passes through, the numbered messages, the point that orders the conflicting requests, and which node supplies the newest data. | |
Trade-off | Latency in legs, traffic, storage at H, verification cost, and the alternative design with its own cost. | |
Evidence | How you would know it works: a numbered trace with a state/value table, a counter, an assertion, a scoreboard value check, a model. |
The rule: an answer is not finished until each part has at least one concrete sentence. The order matters less than coverage, but saying the assumptions first stops you from defending a trace that only works on an ordered bus when the interviewer meant a directory on an unordered network.
The mechanism is already traced in Simultaneous Upgrades: C0 and C1 both start in S / 0, C0's GetM A is accepted first, C1's GetM B is queued, C1 is invalidated in SM^D and later receives Data(1) with M, then stores 2. Here we grade two answers against it, keeping that lesson's roles: C0 wins, C1 waits.
# not-run: illustrative interview answer
"That's a race condition. The coherence protocol, MESI, makes sure only one
of them wins. The other one gets invalidated and then it retries. The bus
handles the ordering, so it is always consistent."Phrase | Framework part | What is wrong or missing |
|---|---|---|
"MESI" | Assumption (partial) | Names a protocol but not snooping or directory, the ordering, the start state, or who collects acks. |
"only one of them wins" | Mechanism (vocabulary) | True, but says nothing about where the order is decided or what the loser does while waiting. |
"gets invalidated and then it retries" | Mechanism (half right) | Misses that the loser, having lost its S copy, now needs Data with the value 1, not permission only. "Retries" assumes a NACK policy the answer never chose. |
"the bus handles the ordering" | Assumption (unstated) | Silently switches to an ordered snooping bus, which is a different model from a directory. |
"always consistent" | Imprecise term | Confuses coherence with consistency: see Coherence Is Not Consistency. |
(nothing) | Trade-off, Evidence | No cost, no alternative, no way to check. |
# not-run: illustrative interview answer
Assumption: "I'll assume MSI with a directory at a home H that serializes
requests per line, reliable delivery, no FIFO order, Inv-Acks collected at H,
and both cores holding X in S with value 0. If they started in I the order is
decided the same way, there is just no copy to invalidate."
Mechanism: "Both send GetM and enter SM^D. H accepts one first, say C0's: that
acceptance is the serialization point, and C1's GetM is queued. H sends Inv to
C1. C1 is still in SM^D, so it gives up its copy, keeps its store pending, goes
to IM^D and acks. H then sends C0 permission-only Data, and C0 stores 1. For
C1's request H forwards Fwd-GetM to C0, C0 sends Data(1) back to H, and H sends
C1 Data(1) with M, so C1 stores 2. There is never a moment with two writers,
and the writes are ordered 1 then 2."
Trade-off: "Queueing at H costs a pending-entry slot but avoids retry traffic.
NACK and retry frees H but can livelock or starve without a fairness rule.
C0 must do its store before answering the forward, or the line can pass back
and forth with no store completing. If the cores were writing different bytes,
this is false sharing and the fix is data layout, not protocol."
Evidence: "I'd check SWMR as an assertion on every cycle, have a scoreboard
check that C1's store follows the value 1 in a single write order for X, cover
the event 'Inv arrives in SM^D', and run a directed test that sends both GetMs
together. In silicon, a line-transfer counter for X would show the hand-off."Part | What earns the credit |
|---|---|
Assumption | Protocol, directory, home ordering, no FIFO, ack collection, start state, and how the answer changes if the start is I. |
Mechanism | Names the serialization point (H's acceptance), the loser's transient path SM^D to IM^D, and that the loser needs data, not just permission. Matches Simultaneous Upgrades step for step. |
Trade-off | Queue versus NACK (Retries, NACKs and Credits), the store-before-forward livelock rule (Deadlock, Livelock, Starvation), false sharing (True Versus False Sharing). |
Evidence | An assertion, a value check, a race coverage point and a directed test (Race and Cross Coverage, Directed Race Stress), plus a counter for silicon (Coherence Performance Counters). |
The strong answer is about a minute of speech. It does not mention every lesson; it shows the interviewer where each part can be probed. A good interviewer then asks a follow-up in the weakest part, so make that part deliberate rather than accidental.
Because H served C0's request first and invalidated C1's S copy to do it. When B is finally served, C1 is in IM^D with no bytes. The answer must notice that the request type at issue time (upgrade) no longer matches what C1 needs at grant time (data plus M). That observation is the mechanism credit that separates level 2 from level 1.
Whether they write the same location or different bytes of the line. The protocol mechanism is identical because permissions cover the whole line, but different bytes means false sharing: both values must survive (C1's Data carries C0's byte along with the rest of the line), and the trade-off answer is data layout rather than protocol.