Every earlier part assumed caches that never sleep, one clock and perfect storage. Real chips break all three. A cache that powers down still holds permissions H has recorded; a message that crosses a clock boundary can be torn or reordered by a careless crossing; and a flipped state bit is a coherence bug, not just a data error. This part shows how each of these physical effects can break the invariants of Parts 1 to 4, and the standard mechanisms that keep them intact.
Lesson | After it you can... |
|---|---|
List what a cache must write back, release and drain before it loses power. | |
Order the steps that take a cache out of the domain and back. | |
Choose between power-off, retention with flush and wake-on-snoop. | |
Resolve a forward that crosses a cache's departure. | |
Carry each message class safely across a clock boundary. | |
Size a crossing buffer from the credit round trip. | |
Reset a link without losing an Inv-Ack or a newest value. | |
Recognise crossing bugs and the checks that find them. | |
Explain why metadata errors are coherence bugs and how ECC covers them. | |
Contain an uncorrectable data error to its consumer. | |
Recover conservatively when a directory entry cannot be trusted. | |
Decide what is corrected, contained or fatal. |
The examples keep the course model and add only what each topic needs: a power state for a cache, a clock domain per side of H, or a poison bit on Data. Clock-domain crossing design itself is taught in the CDC and RDC course; this part only uses it.
Because H may still send it an Inv or a forward, and a cache that cannot answer stalls H forever. Keeping data is not the same as keeping the ability to respond: a retained cache must either wake to answer, or leave the domain (flush and tell H it holds nothing) before it sleeps.