Memory Latency and Coherence · cache-coherency

Part 9 · SoC Integration · All levels

Would faster DRAM fix this coherent miss?

First identify its required source and permission work. In a cold MESI snapshot with X = 0 and H U, backing memory is authoritative. In a warm C0 M / 1, C1 I / -, H exclusive(C0), memory = 0 snapshot, C0 must participate. A permission-only upgrade may need no new payload at all. These paths cannot share one universal DRAM-latency multiplier.

Existing course path	Backing-memory work	Other dependency to measure
Cold read	Current data read	Home admission, response delivery and fill acceptance.
Permission-only upgrade	No refill read for the retained value	Invalidation handling and H-collected acknowledgment.
Dirty read under MSI/MESI	Memory update before settled shared completion	Dirty-holder response and protected data acceptance.
Dirty transfer to another writer	No forced memory update in the selected path	Current-data forwarding and exclusive permission handoff.
Default dirty eviction	Write accepted before Put-Ack	WB capacity, memory-side queueing and acknowledgment delivery.

Classifying the executed path determines whether to examine backing service, peer transfer or permission-only work.

Latency attribution follows the actual transaction path.

Use the existing illustrative latency calculation rather than redraw it. Its cold GetS takes 43 illustrative cycles, 30 of them the memory read: that is the path lower DRAM latency directly helps. Its upgrade's 20-cycle serial subtotal contains 0 cycles of memory read, so cutting DRAM read time cannot reduce a term the upgrade never incurred. It could indirectly affect contention, which would be a separate measured effect.

For an eviction-heavy workload, backing delay can fill finite WB entries and backpressure private replacement, causing later demand misses to wait before they even reach H. Separate that queueing effect from the service time of the current demand read. Review the existing controller resources to locate the blocked storage.

Any eventual-completion claim assumes eventual memory service, reliable delivery, protected finite buffers, fair relevant scheduling and eventual receiver acceptance. A maximum-cycle promise additionally needs bounds on refresh/interference, queues and service under the chosen memory contract. A finite average is not such a bound.

Check yourself Can reducing DRAM read latency directly shorten the permission-only upgrade's four message legs?

Not in the selected path. Its retained data needs no backing read. Any improvement would need another changed dependency, such as reduced shared-resource contention, supported by evidence.

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Would faster DRAM fix this coherent miss?

Existing course path	Backing-memory work	Other dependency to measure
Cold read	Current data read	Home admission, response delivery and fill acceptance.
Permission-only upgrade	No refill read for the retained value	Invalidation handling and H-collected acknowledgment.
Dirty read under MSI/MESI	Memory update before settled shared completion	Dirty-holder response and protected data acceptance.
Dirty transfer to another writer	No forced memory update in the selected path	Current-data forwarding and exclusive permission handoff.
Default dirty eviction	Write accepted before Put-Ack	WB capacity, memory-side queueing and acknowledgment delivery.

Classifying the executed path determines whether to examine backing service, peer transfer or permission-only work.

Latency attribution follows the actual transaction path.

Check yourself Can reducing DRAM read latency directly shorten the permission-only upgrade's four message legs?

Not in the selected path. Its retained data needs no backing read. Any improvement would need another changed dependency, such as reduced shared-resource contention, supported by evidence.