No. In the course model H serializes conflicting transactions for X, but C0 can hold M / 1 while H records exclusive(C0) and memory = 0. Serialization means choosing and enforcing an order for conflicting line operations. Data authority identifies the source of the required value. Neither requires H to contain every current payload at all times.
The point of coherence (PoC) is Arm's term (Arm Architecture Reference Manual for A-profile, DDI 0487): the point at which all agents that can access memory are guaranteed to see the same copy of a location. It is a target for cache maintenance (clean or invalidate to PoC), usually memory or a memory-side cache. H is something different: the per-line point of serialization, where conflicting requests for X are put in one order. H can serialize X while the current value sits in C0, so the two points need not coincide. The PoC and PoU definitions are tabulated in Cache Maintenance Operations.
Question | Course answer in the warm MESI X = 1 snapshot | Why separate |
|---|---|---|
Where are conflicts on X ordered? | At H's active/pending work | H need not already have the payload. |
Where is current X? | C0 M / 1 | Memory = 0 cannot answer as current. |
What proves a default dirty eviction reached memory? | H's memory update before Put-Ack | C0's WB entry held the current value until memory accepted it. |
What proves persistence? | No such contract is added here | Volatile memory acceptance alone is not nonvolatile durability. |
Use the existing completion comparison for the default and early Put-Ack examples. The integration question adds a boundary: when may H treat a memory write as accepted? A controller may accept (and H may send Put-Ack) once the write sits in a queue that every later same-address read checks and that keeps the data until DRAM is written. When DRAM is actually written is then invisible to coherence and matters only for persistence. A write queue whose entries later reads do not check is not a valid acceptance point.
The queue rule that makes this acceptance safe (forward or block on a same-address hit) is the subject of Memory-Controller Reordering.
No. C0 may have silently changed a clean exclusive copy into M and written 1. H's metadata directs resolution; it does not rewrite backing bytes.