Direct memory access, or DMA, lets a device transfer memory without the CPU performing each payload load/store. That does not determine its cache-coherence or synchronization contract. Introduce a device D explicitly and identify its path before choosing software maintenance.
Lesson | After it you can... |
|---|---|
Say which clean and invalidate steps a non-coherent device needs, and when. | |
Trace a one-way coherent device read and write through H. | |
Name CXL's three protocols, its device types and who manages coherence. | |
Write the Linux DMA API sequence for each direction and for a descriptor ring. |
Read in order after current-data sourcing and completion boundaries. The CPU caches remain MESI C0/C1. D is an additional named device, not a renamed CPU.
No. Coherence addresses cached data and permissions. Buffer lifetime, operation ordering, atomicity and application synchronization still need a defined contract.