No. An I/O-coherent port is one-way coherent: the device's accesses snoop CPU caches, but the CPU never snoops the device, because the device has no cache. H resolves each device access against C0 and C1 and then forgets it. A device with a coherent cache, covered in the next lesson, has additional obligations for retained permission, snoops and dirty data.
Each device transaction carries a shareable or snoop attribute, set by the device itself or taken from the IOMMU / SMMU page attributes for that address. Only attributed transactions are snooped. A transaction without the attribute takes the non-coherent path even through the same port, so the same buffer can be coherent for one mapping and not for another.
Warm start (MESI): C0 M / 1, C1 I / -, H exclusive(C0), memory = 0. D issues a snooped read of X. D is the device acting through H: H sends Fwd-GetS(X) to C0 on D's behalf, C0 sends Data(1) to H, H writes memory = 1 and returns Data(1) to D.
Step | C0 state / value | C1 state / value | H directory | Memory | Newest data |
|---|---|---|---|---|---|
0. Warm start | M / 1 | I / - | exclusive(C0) | 0 | C0: 1 |
1. D's snooped read at H | M / 1 | I / - | exclusive(C0), pend read D | 0 | C0: 1 |
2. Fwd-GetS at C0 | S / 1 | I / - | exclusive(C0), pend read D | 0 | C0: 1, Data(1) in flight to H |
3. Data(1) at H | S / 1 | I / - | exclusive(C0), pend read D | 0 | C0 and H buffer: 1 |
H writes memory | S / 1 | I / - | S{C0}, pend read D | 1 | C0 and memory: 1, Data(1) in flight to D |
4. Data(1) at D | S / 1 | I / - | S{C0}, pend read D | 1 | C0 and memory: 1, D has used its one-time copy |
(assumed) grant delivered | S / 1 | I / - | S{C0} | 1 | C0 and memory: 1 |
End state: C0 S / 1, H S{C0} with no entry for D, memory = 1. D keeps no copy, so there is nothing to invalidate later. A variant lets C0 keep M while supplying a copy: H asks C0 for a snapshot without a downgrade, C0 stays M / 1, H stays exclusive(C0) and memory stays 0. That is legal only because D retains nothing.
A device write to X invalidates CPU copies. If C0 or C1 hold X in S, H sends Inv and collects Inv-Ack. If C0 holds the line dirty and D writes only part of it, H must first recover C0's dirty data with Fwd-GetM, because permissions cover the whole 64-byte line and the other bytes are only in C0. H then merges D's bytes, writes the merged line to memory and records U. From the warm start above, D writes 2 to X:
Step | C0 state / value | C1 state / value | H directory | Memory | Newest data |
|---|---|---|---|---|---|
0. Warm start | M / 1 | I / - | exclusive(C0) | 0 | C0: 1 |
1. D's snooped write of 2 at H | M / 1 | I / - | exclusive(C0), pend write D | 0 | C0: 1 (rest of line dirty in C0), H buffer: D's 2 |
2. Fwd-GetM at C0 | I / - | I / - | exclusive(C0), pend write D | 0 | H buffer: D's 2, Data(1) with C0's line in flight to H |
3. Data(1) at H, H merges | I / - | I / - | exclusive(C0), pend write D | 0 | H buffer: merged line, X = 2 |
H writes memory | I / - | I / - | U, pend write D | 2 | memory: 2 |
4. Write completion at D | I / - | I / - | U, pend write D | 2 | memory: 2 |
(assumed) completion delivered | I / - | I / - | U | 2 | memory: 2 |
Without the snoop, D's 2 would reach memory while C0 still held M / 1. C0's later eviction would write 1 back over 2: the failure that non-coherent software avoids with clean-or-invalidate before the device writes.
Integration property | Question to ask | Not implied |
|---|---|---|
Address coverage | Which buffers and regions use this path? | Every address is coherent. |
Snoop attribute | Does the device or the IOMMU / SMMU page attribute mark this transaction shareable? | Connecting to a coherent port makes every transaction snooped. |
Device caching | May D retain readable or writable copies? | An I/O-coherent transaction permits a device cache. |
Translation | How does the DMA address identify the target? | An IOMMU also reconciles cache contents. |
Software ordering | What publishes payload before notification? | Coherent data automatically orders the doorbell. |
An IOMMU translates and constrains device addresses under its configured mapping. That is a different problem from reconciling a CPU dirty line, although its page attributes may carry the snoop attribute. The DMA API documentation also distinguishes a CPU pointer from a DMA address: the device must be given the address returned by the platform API, not a cast of a CPU pointer.
No. After the read H records S{C0} only. D retains no copy, so there is nothing to revoke later.
Permissions cover the whole 64-byte line. C0 holds the only copy of the other 60 bytes, so H sends Fwd-GetM to recover them, merges D's bytes, writes memory and records U.