A retained device cache becomes part of the permission and current-data problem. If D can hold a writable line, a later CPU request cannot assume memory is current: H must snoop D, and D must answer. This is stronger than the one-way coherent port of the previous lesson.
The reference here is the Compute Express Link Specification, Revision 2.0, Version 1.0. CXL runs three protocols over one link. CXL.io is PCIe-based and carries discovery, configuration and non-coherent DMA. CXL.cache lets a device cache host memory coherently. CXL.mem lets the host access memory attached to the device.
Device type | Protocols | Typical use |
|---|---|---|
Type 1 | CXL.io + CXL.cache | Accelerator with a coherent cache and no host-managed device memory. |
Type 2 | CXL.io + CXL.cache + CXL.mem | Accelerator with a coherent cache and its own device-attached memory (HDM). |
Type 3 | CXL.io + CXL.mem | Memory expander, no device cache. |
Coherence is host-managed and asymmetric. The host's home agent owns coherence for host memory, in the role H plays in this course. The device cache holds lines in MESI states, issues device-to-host requests to obtain lines and must answer host-to-device snoops. CXL.cache has three channels in each direction: D2H Request, Response and Data, and H2D Request, Response and Data. Device cache states are MESI; message names differ from the course's GetS / GetM.
Return to the warm snapshot C0 M / 1, C1 I / -, H exclusive(C0), memory = 0. If D requests X over CXL.cache, the host's home agent snoops C0 exactly as H does for any requester, and D may then hold the line. Once D holds it, a CPU request for X makes the host send an H2D snoop to D, and D answers on its D2H response and data channels. The device is a cache participant tracked by the host, never a home for host memory.
Host Bias and Device Bias are modes of a Type 2 device's own memory (HDM), not of CXL.cache access to host memory. In Host Bias the device reaches its own memory through the host, which resolves coherence first. In Device Bias the host is known not to cache the line, so the device reaches its own memory without consulting the host. Host access to a Device Bias line requires a bias flip to Host Bias first.
No. Cache coherence does not say the device has finished its operation or stopped using that storage. Lifetime and completion remain separate contracts.