H's buffer (early Put-Ack) or the memory controller's write queue can hold the current value while DRAM is old, and the controller can reorder commands to different addresses without changing any coherence permission. This topic separates H's per-line serialization from the controller's scheduling, shows the write-queue address check that keeps same-address order, and then attributes latency.

Read after dirty writeback, writeback buffers and completion boundaries. The course default writes memory before Put-Ack. Once 'memory written' means accepted into a checked write queue (Point of Coherence lesson), H can issue a new read of X while an older write to X is still queued. The reordering lesson shows what keeps that safe.

Related topics

• Shared course model

• Prerequisite: default and early acknowledgment boundaries