Yes. The data-value invariant says each epoch starts with the newest value, the end value of the last write epoch (see the glossary for epoch). H can choose every epoch correctly and still hand a cache an old value if the queues below it lose that value. A correct H decision needs a downstream path that preserves its current bytes and matches replies to the work that requested them.
Use the previous lesson's write-queue model: X and Y (a different line) start at memory = 0, and queue acceptance lets the controller hold W X = 1, W X = 2 and R X at once. Each row below is a way the controller's queues can break the same-address rule. These are implementation defects, not legal outcomes of a weak memory model. If H waited for DRAM itself before the next access to X, none of them could arise.
Hazard | Concrete failure to detect | Contract obligation |
|---|---|---|
Read-after-write | R X served from DRAM = 0 while W X = 1 waits in the write queue, H grants S with 0 | Check reads against the write queue by address, forward the youngest matching data or hold the read until the write issues. |
Write-after-read | A younger W X = 2 drains before an older R X that should return 1, so the read returns 2 | An older same-address read issues, or takes its data, before a younger write to that address drains. |
Write inversion | Old accepted W X = 1 overwrites newer W X = 2, DRAM ends at 1 | Keep same-address write order in the write queue, or merge so the youngest data wins. |
Stale response reuse | Reply for an old read finishes a newer request for X | Match active work identity, not address alone. |
Partial-line merge | A later word update reconstructs other words from stale bytes | Preserve untouched current bytes under the write-mask contract. |
Premature buffer reuse | Accepted newest bytes overwritten before safe handoff | Keep protected storage until the defined acceptance event. |
Link to late acknowledgments and data for existing matching rules, and writeback buffers for source retention. Do not invent generation tags as a universal wire requirement: identity can be implemented in different ways, but the association must be unambiguous under permitted outstanding work.
For a partial-line example, take a second word W at byte offset 8 of X's line (Y stays a different line in this topic). A partial write of W must keep the newest X, not an X rebuilt from memory = 0. The whole-line traffic checker already injects that neighbouring-value loss; this lesson adds where a memory-side merge could reintroduce it: the merge must take untouched bytes from the youngest queued write to the line, not from DRAM.
No. A fence constrains operation ordering under its architecture. It cannot repair a downstream implementation that violates its accepted ordering/data contract.