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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
  • Performance and Scalability12
  • Real Protocols12
  • SoC Integration12
    • LLC Data and Directory Policies
    • Devices and DMA
      • Coherent Versus Non-Coherent DMA
      • I/O-Coherent Ports
      • Device Caches and CXL.cache
      • Software Maintenance for DMA
    • The Memory-Controller Boundary
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
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‹Devices and DMA
  1. Topics
  2. Cache Coherency
  3. SoC Integration
  4. Devices and DMA
  5. Coherent Versus Non-Coherent DMA

Part 9 · SoC Integration · All levels

Coherent Versus Non-Coherent DMA

Classify the path for a specific buffer before predicting what a device read or CPU read can observe.

Will the device see the CPU's dirty cache data?

Add device D to the two-core system. Use MESI for C0/C1 and a software handoff that stops CPU writes before D consumes the buffer. Warm start from X = 0: C0 M / 1, C1 I / -, H exclusive(C0), memory = 0. A coherent device read path snoops C0 and returns 1. A non-coherent path reads memory directly and returns the stale 0 unless software has cleaned the line first.

The Linux DMA guide distinguishes coherent and streaming mappings and explains why drivers use the DMA API. The clean itself is the trace already shown in Cache Maintenance Operations: PutM, H writes memory, Put-Ack, and the operation is complete. It is not redrawn here. The sourcing lesson supplies the coherent mechanism.

Case

What software or hardware does

Result in the X example

Coherent DMA read

The coherent path snoops C0 on D's behalf, C0 supplies its dirty 1

D reads 1. See I/O-Coherent Ports for the trace.

Non-coherent DMA read

Software clean of X to the point of coherence (here memory)

memory = 1 and the clean has completed before the doorbell write, so D reads 1.

Non-coherent D write of 2, then CPU read

Clean or invalidate X before D starts, invalidate X after D's completion

C0 invalidated, so the CPU load misses and reads D's 2 from memory.

A coherent path snoops CPU caches. A non-coherent path needs a clean before the device reads, or clean-or-invalidate before and invalidate after the device writes. Both still need ordering and completion.
Coherent and non-coherent paths differ in data reconciliation, not in the need for a software handoff.

For the non-coherent snapshot, a device read of memory = 0 is a stale device input caused by a missing clean. It is not evidence that the CPU coherence controller lost X = 1: C0 still has it. Conversely, making the device path coherent would not fix an incorrect descriptor address or a device started before the producer finished.

Rule for a non-coherent device: clean the buffer's lines to the point of coherence before the device reads. Clean or invalidate before the device writes, so that a dirty CPU victim cannot later overwrite the device's data. Invalidate after the device completes and before the CPU reads, because speculative fills may have refetched the old value during the transfer. Use Part 3's clean and invalidate definitions; the platform API chooses the instructions.

Common pitfall

Treating physical memory address equality as proof that CPU and device use the same coherent observation path.

Interview

Start with who produced the newest bytes, who consumes next, and which path connects them. Then state the clean or invalidate step for each direction and the completion evidence.

Check yourself Why can a device read 0 while C0 still correctly holds 1?

A non-coherent device reads memory directly. If software did not clean X to the point of coherence before the doorbell, memory still holds 0. C0's 1 is not lost: the stale device input and a lost CPU value are different diagnoses.

Related topics

  • Shared course model

  • Part 3: clean and invalidate

  • Direction and buffer handoff

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See also

  • Device Caches and CXL.cache
  • Software Maintenance for DMA