A completion observation proves a named event, not every event downstream. Local instruction retirement, coherent visibility, home acceptance, backing-memory update and persistence are different claims. Their ordering and reporting mechanisms depend on the operation and architecture.
Use MSI and the existing dirty writeback trace, including its named early Put-Ack variant. Do not confuse it with the default, which writes memory before Put-Ack. Warm-up from X=0, as in that trace: C0 stored 3, so C0 is M / 3, C1 I / -, H exclusive(C0), memory=0. A read can already obtain 3 by coherent forwarding.
Rather than redraw that trace, compare its evidence boundaries. During eviction C0 is MI^A / 3 with data in its writeback buffer (WB), not I with forgotten dirty bytes. In the early Put-Ack variant H acceptance lets C0 release WB while H still protects 3 and memory remains 0. In the default Put-Ack instead follows memory acceptance. The acknowledgment's chosen contract is what matters.
Observed event | Establishes in this example | Does not establish |
|---|---|---|
Coherent store before the trace | The new value is available through the coherent source contract. | Backing memory has been updated. |
Early-variant Put-Ack delivered | H accepted dirty responsibility and source WB may be reused. | Memory is already current or persistent. |
Default Put-Ack delivered | Memory already accepted the write and source WB may be reused. | Nonvolatile persistence. |
Backing update accepted | Memory contains X=3 under this modelled target. | Nonvolatile persistence or software notification by itself. |
Local retirement, if reported by an ISA | Only the architecture-defined retirement contract. | A universal position relative to every remote observation. |
A store is globally visible when its buffered entry is written into a line C0 holds in M. H granted M only after every Inv-Ack, so no other cache can still return the old value. If software needs to wait for the memory target, a real architecture/platform must provide the corresponding reporting and ordering mechanism. The diagram does not fabricate one. Coherent visibility can precede that acceptance because 3 was reachable through the dirty-responsible holder or H's buffer. The newest value must remain protected at every handoff.
A performance counter or trace should label which interval it measures. Request-to-grant, store-issue-to-global-visibility, writeback-acceptance-to-memory and persistence latency are not interchangeable. Two teams can report different 'completion latencies' while measuring different endpoints.
Yes. The coherent source can be C0 or a protected H buffer while memory lags. Coherent visibility does not require immediate backing-memory update.