A coherent protocol determines how values and permissions for a location are preserved. A memory model constrains which combinations of observations across operations are permitted. This topic connects those contracts without equating a cache state diagram with an ISA specification.
Lesson | After it you can... |
|---|---|
Explain a coherent execution that SC forbids across locations. | |
Separate store issue, local forwarding and global visibility. | |
Enumerate rather than guess the outcomes of two small tests. | |
Name the architectural model and identify evidence needed for a claim. |
Read in order. The architectural examples extend the two-core course system with Y in a different 64-byte line. Both locations start at 0, with no cached copies, unless stated otherwise.
No. Store buffering, speculation and architectural ordering constraints are separate from a line's permission transfer. SC makes a global program-order promise that coherence alone does not.