Name the architecture/model, instruction forms, memory type, initial values and ordering constructs. 'A weak CPU can reorder anything' is not a specification. Weak models preserve particular dependencies, same-location constraints and synchronization relationships; the exact rules matter.
Published model | Reference | Question to ask |
|---|---|---|
Armv8-A AArch64 architectural memory model | Arm Architecture Reference Manual for A-profile architecture (DDI 0487), chapter "The AArch64 Application Level Memory Model" | Which loads/stores, dependencies and barriers constrain the execution? |
RISC-V RVWMO, version 2.0 | RISC-V Unprivileged ISA specification, chapter "RVWMO Memory Consistency Model" | Which preserved-program-order, load-value and atomicity rules apply? |
RISC-V Ztso / RVTSO | A separately selected stronger architectural contract | Is the implementation actually claiming this extension rather than baseline RVWMO? |
These are architectural contracts, not vendor pipeline claims. Use the published formal model and a matching litmus tool to decide architecture-specific cases, and record its version and test encoding.
Reuse SB and MP from the previous lesson: X and Y in separate lines, X = Y = 0 initially, C0 and C1 using plain loads and stores.
Model, X = Y = 0 initially, plain loads and stores, no fences or dependencies | SB r1 = r2 = 0 | MP r1 = 1, r2 = 0 |
|---|---|---|
SC | Forbidden | Forbidden |
TSO | Allowed | Forbidden |
Armv8-A | Allowed | Allowed |
RVWMO | Allowed | Allowed |
Under Armv8-A and RVWMO the writer's two stores to different addresses may become visible out of order, and the reader's two loads may be performed out of order. MP needs ordering on both sides. A shareability domain is the set of agents an ordering applies to; ISH, inner shareable, covers all the cores of a normal coherent system.
MP side | Armv8-A | RVWMO |
|---|---|---|
Writer, between W(X) and W(Y) | DMB ISH, or make W(Y) a store-release STLR | FENCE w,w, or make W(Y) an amoswap with .rl |
Reader, between R(Y) and R(X) | DMB ISH, LDAR for R(Y), or an address dependency from r1 to R(X) | FENCE r,r, make R(Y) an LR or AMO with .aq (base loads carry no .aq bit), or an address dependency from r1 to R(X) |
Armv8-A is other-multi-copy-atomic (since the 2017 revision of the Arm ARM): a store seen by one other core is seen by all others. The issuing core may see its own store early through forwarding from its store buffer. RVWMO is multi-copy atomic in the same sense. The invalidation protocol of this course provides that property directly: H collects every Inv-Ack before granting M, so once any core can read the new value from the M copy, no other cache can still return the old one. An update protocol, which pushes new values to sharers one at a time, or a store buffer shared between hardware threads of one core can break it. The IRIW litmus test (independent reads of independent writes) detects the difference: two readers that disagree about the order of two writes to different locations.
Coherence invariants remain necessary underneath the architecture. A protocol that loses X's dirty value is not excused by weak ordering. Conversely, a weak-model-allowed observation is not proof that a cache supplied the wrong epoch value. A useful review keeps those two failure categories separate.
No. The reader's two loads may still be performed out of order. The reader also needs FENCE r,r, .aq on the flag load, or an address dependency from the flag value to the payload load.