An out-of-order core can obtain a load's value long before it knows whether that value may become architectural. Coherence messages keep arriving while the load waits, and squashing the load does not cancel the coherence transaction that fetched its line. These lessons show how a core uses Inv and Fwd-GetM to keep its memory model, and what it must still finish after a squash.
Lesson | After it you can... |
|---|---|
Explain how a TSO core keeps load-load order by checking its load queue against Inv, Fwd-GetM and its own evictions. | |
Trace the replay decision on MP and say which events are compared against the load queue. | |
Follow a reservation through Inv, eviction and SC, and state the RISC-V constrained-loop rules. | |
Classify a bad committed result and collect the first evidence for each bug class. |
Read in order, after the barriers and atomics lessons. The examples use MSI on the course model and the MP test from the litmus lesson.
No. H has C0 pending or recorded as a sharer. C0 must complete the transaction: install S, or install and then evict with PutS and wait for Put-Ack. Only the register result is discarded.