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Course contents

  • How to Use This Course
  • Reading Path
  • Cache Coherency Glossary
  • The Shared Course Model
  • Cache Coherency Revision Sheet
  • Why Coherence Exists8
  • States and Protocols12
  • Transactions12
  • Races and Controller Design8
  • Progress and the Fabric16
  • Ordering and Synchronization12
    • Memory Models and Protocols
      • Coherence Is Not Consistency
      • SC, TSO and Store Buffers
      • Litmus Tests: SB and MP
      • Weak Models: Arm and RISC-V
    • Barriers, Fences and Completions
    • Speculation, Replay and Recovery
  • Performance and Scalability12
  • Real Protocols12
  • SoC Integration12
  • Power, Clocking and Reliability12
  • Verification12
  • Debug and Bring-up12
  • Interview and Design Review17
  • Capstone: A Coherent Model Lab5
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‹Memory Models and Protocols
  1. Topics
  2. Cache Coherency
  3. Ordering and Synchronization
  4. Memory Models and Protocols
  5. SC, TSO and Store Buffers

Part 6 · Ordering and Synchronization · All levels

SC, TSO and Store Buffers

Explain store issue, FIFO visibility and same-core forwarding in the operational subset used by the exercises.

On this page

    Has a store happened when its instruction is issued?

    That depends on which event you mean. An instruction can enter a local store buffer before the store joins the shared memory order. This lesson uses abstract SC and FIFO-buffer TSO for ordinary aligned memory operations only, with X=Y=0 initially and no caches holding either line. It does not model device memory or every instruction in an ISA.

    A store buffers locally before draining, and a local load forwards from the newest same-address buffered store when one exists.
    FIFO is an explicit property of the architectural TSO store buffer, not a FIFO assumption about the course interconnect.

    Operation

    SC exercise

    TSO exercise

    Store

    Update shared memory when that operation takes its place in the total order.

    Append to the issuing core's FIFO; a separate drain updates shared memory.

    Load

    Read the latest preceding shared-memory write in the SC order.

    Forward from the newest own matching buffered store, otherwise read shared memory.

    Program order

    Every operation follows the preceding operation of its core globally.

    Core issue stays ordered, but a different-address load can precede visibility of an older store.

    Two small predictions

    Prediction A: C0 issues W(X)=1 then R(X), starting X=0. With no other writer to X, both SC and this TSO model require the load to return 1. TSO obtains it through same-address forwarding if necessary. Prediction B: the SB test from the previous lesson can return 0,0 under TSO, because each load addresses the other location, not its own buffered one.

    The store buffer's FIFO order also matters for message passing. With X=Y=0 initially, C0 issues W(X)=1 then W(Y)=1, while C1 issues r1=R(Y) then r2=R(X). In this SC and TSO subset, r1=1,r2=0 is forbidden: observing the Y store implies the earlier X store has become visible, and the reader's loads remain ordered. A model allowing different reorderings needs a separate analysis.

    The Owens, Sarkar and Sewell x86-TSO report formalizes an operational write-buffer model. Our enumerator covers a small ordinary-load/store subset, not the complete report or an arbitrary processor implementation.

    Common pitfall

    Treating FIFO store-buffer order as evidence that interconnect messages arrive FIFO. The architecture can require ordering while hardware implements it with explicit completion dependencies over an unordered fabric.

    Interview

    Distinguish three events: issue a store, satisfy a same-core load from it, and make the store globally visible. One vague 'completed' label cannot describe all three.

    Check yourself Can a TSO load of X ignore its own pending store X=1 and read the old globally visible 0?

    Not in this operational subset. It must forward the latest matching own buffered value. Bypassing a different address is the Store-to-Load relaxation used by SB, not permission to ignore an older same-address store.

    Related topics

    • Shared course model

    • Next: enumerate outcomes

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    See also

    • Weak Models: Arm and RISC-V