A cache cluster and its home H often run on different clocks. Every coherence message then passes through a clock-domain crossing, and the crossing becomes part of the protocol: it can add latency, it is a buffer with credits, it has to be reset, and it can break the Part 5 progress rules if built carelessly. This topic does not re-teach synchronizer design; the CDC and RDC course owns that. It shows what the coherence protocol needs from the crossing.
Lesson | After it you can... |
|---|---|
Give each message class its own asynchronous FIFO and explain why one shared FIFO brings back the response deadlock. | |
Size a crossing buffer from bandwidth and credit round trip, and show what one slot less costs. | |
Reset or retrain a cluster-to-H link without losing an Inv-Ack or the newest data. | |
Name four crossing bug classes, their symptoms and the check that finds each. |
Read in order, after Virtual Networks and Progress and Controller Resources. The model for the whole topic: C0 and C1 sit in one cluster clock domain, H and memory in a home clock domain, and the two clocks are asynchronous.
Yes. CDC sign-off proves that bits cross safely, not which messages share a queue. If requests and responses share one in-order FIFO, a blocked request at its head stops the response behind it, which is the Part 5 cycle rebuilt inside a correctly synchronized structure.