Skip to content
DenseChip
Learn
PracticeCode labInterview

DenseChip

Navigate

Menu

LearnPracticeCode labInterview

Tools

All toolsSV editorCode repoResume
DenseChip

Practice, courses, and chip-design tools in one focused workspace.

LearnPracticeCode labInterviewToolsLearning paths

© 2026 DenseChip

AboutContactPrivacyTerms
Skip to lesson

Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
    • MTBF & Synchronizer Math
    • Two-Flop Synchronizers in Practice
    • Multi-bit CDC Hazards
    • Synchronizer Selection Guide
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
Loading lesson

‹CDC & RDC
  1. Topics
  2. CDC & RDC
  3. Metastability and Synchronizers

Part 2 · Metastability and Synchronizers · All levels

Metastability and Synchronizers

Why flops go metastable, the two-flop synchroniser and its rules, multi-bit hazards, and choosing a pattern.

  • 4topics
  • 16lessons

A signal from another clock domain can change inside the receiving flop's setup-hold window, and the flop then resolves late to an unpredictable value. This section builds the full defence: the metastability mechanism and its MTBF model, the two-flop synchroniser with its rules, why words need protocols, and how to choose a pattern.

Learning path through the metastability and synchronizers topics.
Suggested order. Math first, then the two-flop rules, then multi-bit hazards, then selection.

The four topics

Topic

Lessons

After it you can...

MTBF & Synchronizer Math

4

Explain metastability, state the MTBF model, and choose two versus three stages.

Two-Flop Synchronizers in Practice

4

Apply the synchroniser rules, judge levels versus pulses, and model the window in simulation.

Multi-bit CDC Hazards

4

Explain tearing and skew, and pick Gray, handshake, FIFO, load pulse, or RAM.

Synchronizer Selection Guide

4

Map any crossing type and clock ratio to a pattern and defend its cost.

Tip

Read the topics in order: each one assumes the vocabulary of the previous. The design-view companion is the RTL course lesson on Metastability and Synchronisation.

Check yourself Why does this section come before protocols, reconvergence, and signoff methodology?

Because every later argument rests on it: why synchronisers have their shape, why buses need protocols, and what the tools are actually checking for.

Related topics

  • Up: CDC/RDC course hub

  • Glossary

PreviousNext: MTBF & Synchronizer Math

Up next

Up nextMTBF & Synchronizer Math

Sign in to save progress

Practice this lessonReport an error

See also

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary