Two-Flop Synchronizers in Practice

What this topic teaches

Two-Flop Synchronizers in Practice focuses on closing CDC/RDC risk with mechanism-level reasoning. A two-flop chain lowers metastability propagation risk for level signals, but only when source assumptions, pulse width, and destination sampling are respected. Senior signoff depends on proving behavior with targeted evidence, not just clearing tool warnings.

The senior-engineer question

When single-bit CDC clean rate, pulse capture reliability, latency cycles regresses, can you classify the hazard, identify accountable owners, and choose the smallest fix or waiver backed by evidence?

CDC/RDC SIGNOFF FLOW — Two-Flop Synchronizers in Practice

crossing inventory + reset map
          |
          v
crossing classification (level/pulse/bus/reset)
          |
          v
structure + protocol + reset checks
          |
          v
critical issues + waiver review
          |
          v
fix / validate / regress / signoff

Picture the crossing behavior

Draw the behavior before touching tools. These visuals are the expected whiteboard baseline for reviews and interviews.

Two-flop chain limits

SRC -----> [FF1] -----> [FF2] -----> DEST logic
            async sample    filtered sample

Valid for stable level signals.
Not sufficient for narrow pulses or multi-bit buses.

Crossing sequence

CROSSING FLOW — Two-Flop Synchronizers in Practice

source clock domain -> launch signal -> crossing structure -> destination sample
      |                    |                 |                    |
   source FF           protocol           sync / fifo         destination FF

Key metric: single-bit CDC clean rate, pulse capture reliability, latency cycles

Ownership layers

CDC/RDC OWNERSHIP LAYERS — Two-Flop Synchronizers in Practice

layer                 owns                            common failure
------------------    -----------------------------   -----------------------------
design intent         crossing architecture           wrong topology selected
protocol semantics    req/ack, fifo, ordering        liveness/deadlock bugs
reset behavior        assert/deassert sequencing      boot instability
analysis setup        tool rules + waivers            false confidence
signoff governance    risk acceptance + dashboard     stale critical waivers

Evidence to collect

• Primary metric: single-bit CDC clean rate, pulse capture reliability, latency cycles.

• Primary artifact: CDC structural report, RTL synchronizer pattern list, assertion checks.

• Owners to involve: RTL owner, CDC owner, verification owner.

• At least one reproducer tied to mode/reset/traffic context.

• Decision record: fix, waive, or escalate with rationale.

Ownership map

OWNERSHIP MAP — Two-Flop Synchronizers in Practice

artifact                  owner
----------------------    -------------------------
design intent           RTL owner
verification evidence   CDC owner
signoff decision        verification owner

Every open CDC/RDC issue needs one accountable owner before waiver or fix.

Subpages in this topic

Each topic includes mechanism, I/O contract, metrics, debug, worked example, pitfalls, interview drills, checklist, theory, design tradeoffs, expanded case study, walkthrough, comparison matrix, software view, and silicon impact.

Key takeaways

• Classify crossing/reset hazards before proposing fixes.

• Pair structural results with protocol/reset behavioral proof.

• Treat waivers as bounded risk contracts, not cleanup shortcuts.

Common pitfalls

• Mass-waiving warnings near tapeout.

• Assuming local IP cleanliness guarantees SoC behavior.

• Skipping reconvergence and reset stress after CDC fixes.

CDC/RDC deep dive

Metastability is managed risk, not eliminated risk.

Concept diagram

METASTABILITY FLOW

async event -> first sample may metastabilize
 -> settle window
 -> downstream sample confidence

Metric graph

MTBF TREND

target MTBF ---------
current design   ____/

Reports and artifacts

• MTBF assumptions

• synchronizer inventory

• crossing class summary

• critical waivers

Mini case study

Pulse sync chosen for a level signal caused intermittent stuck state under voltage stress.

Debug branches

• Validate crossing class first

• Check pulse width assumptions

• Audit synchronizer template usage

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?

Key takeaways

• State crossing class, assumptions, and owner with every issue.

• Run structural and dynamic regressions after each fix.

Common pitfalls

• Treating all warnings as equivalent risk.

• Waiving issues without containment evidence.

• Skipping reset and reconvergence stress after CDC fixes.