The two-flop synchroniser is the default answer for a single-bit crossing, and most CDC violations are ways of breaking it. This topic teaches the structure, the rules that keep it intact, which signals it suits, and how to model it in simulation.
Lesson | After it you can... |
|---|---|
Draw the circuit and recite the five usage rules. | |
Spot combinational logic in the path and fix the violation. | |
Decide whether a signal may cross directly or needs a pulse scheme. | |
Model the metastable window in a testbench and read X-propagation results honestly. |
Read them in order: the structure lesson defines the rules, and each later lesson defends one of them.
The first flop may go metastable and is never used; the second samples it one period later and is the only output the design reads.