Precise terms used across the course. Each entry links to the lesson that teaches it. British spelling is used in prose; signal and module names keep their code spellings.
Term | Definition | Where taught |
|---|---|---|
Async FIFO | A first-in first-out queue with independent write and read clocks, decoupled through Gray-coded pointers and synchronised full and empty flags. | |
Asynchronous clocks | Clocks with no fixed phase or frequency relationship, so sampling between them can violate setup and hold at any time. | |
Back-pressure | The consumer slowing or stalling the producer (through full flags, withheld ready, or withheld acknowledge) so no data is lost. | |
Bus tearing | A multi-bit word sampled mid-transition so the captured value mixes old and new bits and matches no value the source ever sent. | |
Clock domain | The set of flops and logic clocked by one clock, including its generated, gated, and muxed variants once classified. | |
Clock group | Clocks declared mutually exclusive so timing analysis does not check paths between them; over-grouping hides real crossings. | |
Clock intent | The written record of every clock, its source and relationships, and which crossings are expected, which setup consumes. | |
Constraint | Timing intent (clocks, exceptions, delay bounds) that analysis and implementation obey; CDC intent maps to constraints per the STA topic. | |
Crossing | Any signal or reset path whose source and destination sit in different clock or reset domains and therefore needs synchronisation or a protocol. | |
Depth sizing | Choosing FIFO depth from burst length, rate mismatch during the burst, and synchroniser latency, written down with its inputs. | |
Domain relationship | How two clocks relate: synchronous, mesochronous or plesiochronous variants, or fully asynchronous; the class decides the legal patterns. | |
Dual-clock RAM | A memory with independent clocks per port, used as a bulk multi-bit crossing with its own pointer or flag discipline. | |
False path | A path exempted from timing checks because it is never exercised functionally; dangerous when applied to real crossings. | |
Formal CDC | Exhaustive checks of crossing protocols (safety and liveness) over all reachable states under stated environment assumptions. | |
Full and empty | FIFO status flags computed from synchronised pointers; full stops the writer, empty stops the reader, both conservatively. | |
Gated clock | A clock ANDed with an enable to save power; the gated domain needs its own crossing discipline at entry and exit. | |
Glitch-free mux | A clock multiplexer that switches sources without runt pulses, normally by stopping, switching, then restarting the clock. | |
Gray code | A counting code in which adjacent values differ in exactly one bit, so a sampled pointer is at worst one step off. | |
Handshake | A request and acknowledge exchange (two-phase toggle or four-phase return-to-zero) that guarantees delivery across domains. | |
Hierarchical analysis | Block-level CDC analysis under stated boundary assumptions, fast enough to run on every change; validated by flat runs. | |
Liveness | The protocol property that every request is eventually answered under the stated environment assumptions. | |
Lost event | A pulse or transaction the destination never sees because it fell between sampling edges or was overwritten. | |
Metastability | The uncertain balancing state a flop enters after a setup or hold violation; it resolves to 0 or 1 given enough settling time, and the chance of it still being unresolved falls exponentially with that time. | |
Metastability injection | Simulation that deliberately perturbs sampled values inside a stated window to exercise downstream tolerance. | |
MTBF | Mean time between metastability-induced failures; dominated by an exponential in resolution time over the flop time constant. | |
Multi-bit crossing | Several related bits crossing together; per-bit synchronisers let them skew, so a protocol (Gray, handshake, FIFO) is required. | |
Mux recirculation | Holding FIFO-style data stable with a destination-side mux loop so one synchronised load pulse captures a coherent word. | |
Pulse synchroniser | A scheme (toggle, stretch, edge detect with spacing rules) that carries single-cycle events across a sampling boundary. | |
Quasi-static signal | A signal stable during normal operation that changes only in stated windows (reset, configuration); safe only under qualification. | |
RDC | Reset-domain crossing: interaction between logic under different resets, centred on release ordering and synchronised deassertion. | |
Reconvergence | Separately synchronised signals meeting again in downstream logic, where skew between branches creates illegal transient combinations. | |
Recovery and removal | The setup-like (recovery) and hold-like (removal) checks on asynchronous reset release relative to the clock. | |
Reset isolation | Holding downstream logic in a known state while its reset domain is inactive or sequencing, so unknown values cannot propagate. | |
Reset sequencing | Releasing domain resets in dependency order (receivers before senders) with readiness checks between steps. | |
Reset synchroniser | A per-domain synchroniser chain aligning reset release to the destination clock; assertion may stay asynchronous. | |
Resolution time | The settling time the first synchroniser flop gets before its output is used; each extra stage adds one destination period. | |
Review gate | A milestone review where design, verification, and signoff owners answer their checklists in writing before the meeting. | |
Signoff dashboard | The tracked metric set (findings by class, fixed versus waived, waiver age, owners, constraint changes) read as trends. | |
Skew | Arrival-time spread between related signals at a capture point, from routing or independent synchroniser delays. | |
Structural analysis | Exhaustive connectivity analysis classifying every crossing against synchroniser and protocol rules; topology, not behaviour. | |
Synchroniser | Two or more destination-clock flops in series giving the first flop settling time; the design uses only the last flop. | |
Synchroniser stages | Stage-count policy per clock speed (two normally, three at very high frequencies or for high reliability); stages buy settling time only. | |
Toggle synchroniser | A pulse scheme converting each source event into a level toggle that the destination synchronises and edge-detects. | |
Valid and ready | A forwarded-flow handshake interface; crossing domains with it needs the valid, ready, and data relationship re-proven. | |
Violation class | A structural finding category (unsynchronised, logic before sync, protocol-less bus, reconvergence, reset, misuse) with its severity. | |
Waiver | A bounded, evidenced, owned, and expiring acceptance of residual risk on a specific finding; never a cleanup shortcut. | |
Waiver evidence | The five waiver fields: finding reference, protocol argument, assertion or simulation proof, constraint reference, owner and expiry. | |
X-propagation | Unknown-value flow in simulation from uninitialised or metastable sampling; honest models state their window and seed. |