A 4-bit binary counter stepping from 0111 (7) to 1000 (8) changes all four bits at once. Each bit travels its own wire with its own delay, and each bit's synchroniser samples and resolves on its own. If the destination clock samples mid-transition, some bits are caught old and some new, and the word read out is neither 7 nor 8.

The 0111 to 1000 example

At the 7-to-8 step the destination edge lands after bits 2:0 have arrived with the new value 000 but while bit 3 is still presenting the old 0 through its extra register stage. The first-stage flops therefore capture 0000: three bits new, the top bit old. One period later the second stage delivers that 0, a value the counter never held, and downstream logic acts on it before the crossing settles to 8.

The waveform below is simulation output for exactly this case: a scripted counter stepping up through 6, 7, 8 and 9 into per-bit synchronisers, where bit 3 passes through one extra destination-clocked register modelling a full slow period of extra wire delay, sampled by a 20 ns clock. The one-period skew is a deliberate exaggeration to make the tear deterministic; real skew is picoseconds, but the old/new mixing it causes is identical.

How to read it: cnt is the source counter. q1 is the first synchroniser stage and sync the second, one stage behind. The four-bit step from 7 to 8 tears: q1 reads 0 at the fifth sample and sync repeats that 0 at the sixth sample before both settle to 8. The steps that do not change bit 3 cross cleanly, because the delayed bit still presents its true value.

What the tools check

Structural analysis flags any multi-bit bus crossing whose bits each carry their own synchroniser with no protocol around it. Review triage treats a torn word as a data-corruption bug, not a marginal MTBF concern: no number of stages per bit removes it.

Related topics

• Why Bitwise Sync Fails

• Safe Patterns Overview