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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
    • MTBF & Synchronizer Math
    • Two-Flop Synchronizers in Practice
    • Multi-bit CDC Hazards
      • Bus Tearing
      • Why Bitwise Sync Fails
      • Skew and Capture Window
      • Safe Patterns Overview
    • Synchronizer Selection Guide
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹Multi-bit CDC Hazards
  1. Topics
  2. CDC & RDC
  3. Metastability and Synchronizers
  4. Multi-bit CDC Hazards
  5. Why Bitwise Sync Fails

Part 2 · Metastability and Synchronizers · All levels

Why Bitwise Sync Fails

Per-bit synchronisers do not synchronise a word, and Gray code and enables alone do not fix every case.

On this page

    Putting a synchroniser on each bit feels thorough: every bit is settled, so the word should be fine. It is not, because synchronising is a statement about one bit's timing, while a word needs all bits from the same moment.

    Each bit resolves on its own

    A synchroniser guarantees each bit eventually delivers a clean old or new value. It says nothing about which bits deliver old and which deliver new on any given cycle. With several bits changing, the destination reads a combination the source never produced, exactly as the tearing lesson showed.

    Why Gray code alone is not enough

    Gray code helps only where it holds: a value that advances one step at a time, so exactly one bit changes per step. A Gray-coded counter is safe to synchronise bit by bit because there is never a second changing bit to mix with. But a counter that can reload, skip, or be written arbitrarily breaks the one-bit rule, and Gray-coded addresses or data that jump are torn just like binary.

    Why an enable alone is not enough

    Qualifying the bus with an enable (“read the bus when enable says valid”) fixes nothing if the enable itself crosses domains naively: the destination may sample the enable and the data at inconsistent moments. A safe enable scheme is really a handshake or a load pulse in disguise, with the data held stable around the synchronised control, which is one of the safe patterns in the next lessons.

    Attempted fix

    What it actually guarantees

    Where it still tears

    More stages per bit

    Cleaner individual bits

    Everywhere: mixing is unaffected.

    Gray code

    One changing bit per step

    Reloads, skips, arbitrary writes.

    A crossing enable

    A control signal arrives

    Whenever data and enable are not held consistent.

    Common pitfall

    Gray code computed combinationally from a binary counter can glitch as the counter bits settle, breaking the one-bit rule before the crossing. Register the Gray value in the source domain and cross the register.

    Check yourself A Gray-coded FIFO pointer crosses bit by bit and the FIFO works. The same scheme is reused for a Gray-coded address bus that the processor can set arbitrarily. What breaks?

    The address can jump many steps at once, changing several Gray bits together, so the destination can capture a torn address. Arbitrary values need a handshake or a load pulse, not Gray code.

    Check yourself Someone proposes three flops per bit “to fix the torn bus”. What is the one-sentence rebuttal?

    Extra stages settle each bit more without coordinating the bits, so the word can still mix old and new values.

    Related topics

    • Bus Tearing

    • Safe Patterns Overview

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    See also

    • Safe Patterns Overview