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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
    • MTBF & Synchronizer Math
      • Metastability Mechanism
      • Resolution Time and MTBF
      • Worked MTBF Example
      • Two or Three Stages
    • Two-Flop Synchronizers in Practice
    • Multi-bit CDC Hazards
    • Synchronizer Selection Guide
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹Metastability and Synchronizers
  1. Topics
  2. CDC & RDC
  3. Metastability and Synchronizers
  4. MTBF & Synchronizer Math

Part 2 · Metastability and Synchronizers · All levels

MTBF & Synchronizer Math

Why flops go metastable, the exponential MTBF model, an illustrative worked example, and two versus three stages.

  • 4topics
  • 4lessons

Every synchroniser argument rests on two facts: a flop sampling a changing input can hover before resolving, and the chance it is still unresolved falls exponentially with the settling time it is given. This topic builds that argument from the mechanism to the stage-count decision.

Lesson

After it you can...

Metastability Mechanism

Explain the setup/hold window and why resolution is probabilistic.

Resolution Time and MTBF

State the MTBF model and the role of each term.

Worked MTBF Example

Work the arithmetic on illustrative parameters and show what a third stage buys.

Two or Three Stages

Choose a stage count and say what extra stages do not fix.

Read them in order: mechanism first, then the model, then the numbers, then the decision.

Check yourself Why does a synchroniser give the first flop a full clock period before anyone looks at its output?

Because the chance the flop is still unresolved falls exponentially with settling time, so one idle period buys an enormous reliability margin.

Related topics

  • Two-Flop Synchronizers in Practice

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See also

  • Two-Flop Synchronizers in Practice
  • Multi-bit CDC Hazards
  • Synchronizer Selection Guide