RDC Signoff

Section goal

RDC methodology, reset-aware verification, chip-level closure, and signoff dashboarding.

How to study this section

1. Start with topic hubs to classify problem shapes.

2. Use mechanism and reports pages to connect risk signals to evidence.

3. Practice debug and worked examples before signoff reviews.

4. Close with checklist and silicon impact before approving fixes or waivers.

Topics

1. rdc-methodology/ — RDC Methodology

2. reset-aware-simulation/ — Reset-aware Simulation

3. chip-level-rdc/ — Chip-level RDC Closure

4. rdc-signoff-dashboard/ — RDC Signoff Dashboard

Related topics

• CDC/RDC course hub

CDC/RDC deep dive

RDC closure must connect IP assumptions to SoC reality.

Concept diagram

RDC CLOSURE

IP reset intent + SoC sequencing -> structural checks -> dynamic stress -> signoff

Metric graph

MILESTONE READINESS

M-2 55%
M-1 82%
M0  100%

Reports and artifacts

• top-level RDC opens

• reset simulation coverage

• chip integration blockers

• waiver backlog

Mini case study

Each IP was locally clean, but top-level sequencing violation created cross-subsystem boot intermittency.

Debug branches

• Audit subsystem assumptions

• stress chip-level reset scenarios

• close ownership gaps

Senior review question

Ask: what evidence proves this risk is closed for silicon, not just tool-clean?