Single-bit synchronisers carry stable levels; everything else needs a protocol. This section teaches the signoff and architecture view of the four standard crossings: pulse synchronisers for events, handshakes for occasional words, async FIFOs for streams, and the verification that proves each of them. How to design these structures is taught in the CDC handshakes and async FIFO RTL lessons, which this section links to instead of repeating.
Lesson | After it you can... |
|---|---|
Explain the loss mechanism for a short pulse into a slower clock. | |
State the toggle rules, including the no-early-re-toggle rule. | |
Judge when stretching is acceptable instead of a toggle. | |
Specify and check the minimum gap between pulses. | |
Walk through the four steps and say why levels make it safe. | |
Trade latency and throughput against the four-phase variant. | |
Explain why plain valid/ready is not CDC-safe and what to wrap it in. | |
Compute round-trip cost symbolically in source and destination cycles. | |
Say what makes the pointer crossing safe and what a check looks for. | |
Explain why conservative flags are safe in both directions. | |
Size depth from burst length, rates and synchroniser latency. | |
Reset both sides correctly and read the tool expectations. | |
Write runnable checkers for pulse, handshake and FIFO protocols. | |
Say what formal proves for crossings and what it assumes. | |
Plan stall, back-pressure and rate-mismatch scenarios. | |
Inject capture-window randomness and read the result honestly. |
Suggested order: work through the four topics in the order shown above, then attempt the section as a review pass: for each crossing in a real design, name its structure, its rule, its check and its test.
A four-phase handshake; its cost is counted in the latency-and-throughput lesson (about 2N + 2M cycles per word, symbolically).