Correctness picks the shortlist; cost picks the winner. The table compares the patterns on the four budgets every crossing spends: latency added, throughput allowed, silicon area, and the effort to verify it.
Pattern | Latency | Throughput | Area and verification |
|---|---|---|---|
Two-flop synchroniser | 2 to 3 destination cycles. | One level change per 2+ cycles. | Two flops; lightest review. |
Three-flop synchroniser | One more cycle than two-flop. | Same as two-flop. | One more flop; same checks. |
Toggle plus edge detect | 2 to 3 slow cycles per event. | One event per latency window. | A toggle flop plus detector; spacing proof needed. |
Handshake | A full round trip per word. | One word per round trip. | Control logic both sides; protocol assertions required. |
Async FIFO | Pointer sync latency on flags. | Burst rate of the memory. | Memory plus pointers; depth, reset, and flag verification. |
Load pulse with held data | Pulse sync latency per write. | Rare writes only. | Holding logic; hold-window argument per crossing. |
Dual-clock RAM | Synchroniser latency on handover. | Memory bandwidth. | A macro plus ownership proof; heaviest review. |
Match the data rate to the throughput column first: streams need FIFOs or RAM, occasional words fit handshakes, rare settings fit load pulses. Then check latency against the protocol budget, remembering each extra synchroniser stage adds a cycle in each direction of a handshake loop. Area decides last, because a cheap pattern with the wrong throughput is not a saving.
Verification effort deserves equal weight with silicon: a handshake without protocol assertions, a FIFO without a depth argument, or shared RAM without an ownership rule will each cost more in signoff debate than a slightly larger but self-evidently correct structure.
The handshake cannot meet the rate: one word per six cycles falls short of one per four. Move to an async FIFO, which pipelines words at memory bandwidth.
In a handshake loop the extra cycle delays every transfer in both directions, compounding per word. On a plain level it is a one-time two-to-three-cycle delivery delay.