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Course contents

  • How to Use This Course
  • Reading Path
  • CDC/RDC Glossary
  • CDC/RDC Metrics Reference
  • CDC/RDC Interview Prep
  • CDC/RDC Signoff Cheatsheet
  • Clock Domains and Failure Modes8
  • Metastability and Synchronizers16
    • MTBF & Synchronizer Math
    • Two-Flop Synchronizers in Practice
    • Multi-bit CDC Hazards
    • Synchronizer Selection Guide
      • Decision Matrix
      • Slow-to-Fast Crossings
      • Fast-to-Slow Crossings
      • Cost of Each Choice
  • CDC Protocols and Handshakes16
  • Reconvergence and Gray Coding16
  • Reset Domain Crossing16
  • Architecture and Design Rules16
  • CDC Signoff Methodology24
  • RDC Signoff16
  • Debug and Case Studies11
  • CDC and RDC Interview Prep30
  • Capstone: Sign Off a Multi-clock Peripheral4
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‹Synchronizer Selection Guide
  1. Topics
  2. CDC & RDC
  3. Metastability and Synchronizers
  4. Synchronizer Selection Guide
  5. Decision Matrix

Part 2 · Metastability and Synchronizers · All levels

Decision Matrix

The main table: crossing type versus clock ratio, with the recommended pattern and the main hazard, plus a decision flow.

Two facts decide the pattern: what crosses (a level or an event, one bit or many) and how the clocks relate. The table gives the recommended pattern for each combination and names the hazard you must still handle.

Crossing type

Slow-to-fast

Fast-to-slow

Unknown ratio

Single-bit level

Two-flop synchroniser; hazard: hold time margin.

Two-flop synchroniser; hazard: level must outlast sampling.

Two-flop synchroniser; hazard: assume the worst ratio both ways.

Single-bit pulse

Two-flop synchroniser if the pulse spans two fast periods; hazard: marginal widths.

Toggle or stretch scheme; hazard: lost pulse.

Toggle (pulse) synchroniser with a minimum-spacing rule; hazard: assume the worst ratio both ways.

Multi-bit data word

Handshake; hazard: data must hold through acknowledge.

Handshake; hazard: same, plus slower round trip.

Handshake; hazard: never assume a ratio.

Multi-bit counter

Gray plus per-bit sync; hazard: must step one at a time.

Gray plus per-bit sync; hazard: sampling skips values.

Gray plus per-bit sync; hazard: jumps forbidden.

Streaming data

Async FIFO; hazard: depth for bursts.

Async FIFO; hazard: depth plus slow-side throughput.

Async FIFO; hazard: size for the worst ratio.

Configuration bus

Load pulse with held data; hazard: hold through capture.

Load pulse with held data; hazard: same.

Load pulse with held data; hazard: same.

Reset

Reset synchroniser; hazard: deassertion racing the clock.

Reset synchroniser; hazard: same.

Reset synchroniser; hazard: same.

Decision flow

Flowchart from crossing type to synchroniser pattern.
Decision flow: bit count first, then signal kind, then the matching pattern.

Unknown ratio is a first-class column, not an afterthought: IP, configurable dividers, and DVFS mean the ratio at signoff time may not be the ratio in the field. When the ratio can change, choose the pattern that is correct for all ratios and verify against the worst one.

Common pitfall

The matrix recommends a pattern, not a waiver. Each cell's hazard column is the review question for that crossing: the design must show how it handles exactly that hazard.

Check yourself A single-bit pulse crosses from a fast domain to a slower one of unknown exact ratio. What does the matrix say, and what is the main hazard?

A toggle or stretch scheme, because a plain synchroniser can lose the pulse between sampling edges. The hazard is the lost pulse; spacing and stretch are sized for the slowest allowed destination clock.

Check yourself Why does the unknown-ratio column never recommend a plain pulse synchroniser for fast-to-slow?

Because correctness would rest on a width assumption about a ratio you do not know. Toggle and handshake schemes are correct for any ratio, so they are the only safe defaults.

Related topics

  • Slow-to-Fast Crossings

  • Fast-to-Slow Crossings

  • Cost of Each Choice

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See also

  • Fast-to-Slow Crossings
  • Cost of Each Choice