Crossing into a slower clock is the dangerous direction: the destination samples rarely, so short events fall between edges and disappear. Every fast-to-slow rule exists to make sure each event is still present when an edge finally comes.

Rules

1. Stretch every pulse past two destination periods before a plain synchroniser, measured against the slowest destination mode.

2. Prefer a toggle scheme where the ratio is wide or unknown: flip a bit per event, synchronise the level, and detect edges on the slow side.

3. Space events apart by more than the synchroniser latency plus the detector width, so pulses never merge.

4. Hold handshake data stable until the slow side's acknowledge returns, however long that takes.

Runnable example: toggle crossing

The testbench below sends four fast events as toggles through a slow-domain synchroniser with an edge detector, and checks that four slow pulses arrive. Event spacing is 100 ns against a 30 ns slow clock, comfortably wider than the synchroniser latency.

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`timescale 1ns/1ps

// Fast-to-slow event crossing: the event toggles a bit, the toggle crosses on a
// two-flop synchroniser, and an edge detector in the slow domain recovers one pulse.
module toggle_sync (input logic clk_s, input logic tog_f, output logic pulse_s);
  logic q1 = 1'b0, q2 = 1'b0, q2_d = 1'b0;
  always_ff @(posedge clk_s) begin
    q1 <= tog_f;  q2 <= q1;  q2_d <= q2;
  end
  assign pulse_s = q2 ^ q2_d;          // one slow cycle high per toggle
endmodule

What the tools check

Structural analysis recognises the toggle flop, the two synchroniser flops, and the edge detector as one scheme, and flags a bare pulse wire into a slow domain. The review checks stretch widths against the slowest mode and event spacing against the synchroniser latency.

Related topics

• Slow-to-Fast Crossings

• Decision Matrix