Resets are designed in the RTL course and signed off here. Each clock domain can release perfectly on its own clock while the chip still fails: releases landing in recovery/removal windows, domains waking in the wrong order, outputs of a reset domain mistaken for live data, and signals crossing between reset domains with no protection. This section teaches the signoff, structural-check, and debug view of those failures.
Topic | Lessons | After it you can... |
|---|---|---|
4 | Explain the release hazard, draw the synchroniser, state recovery/removal, and read the release waveform. | |
4 | Order releases across domains, isolate reset domains, and scope each reset kind. | |
4 | Define an RDC crossing, read finding categories, and triage a findings list. | |
4 | Map symptoms to causes, read a glitchy release, and work the checklist. |
The RTL course teaches the design side: Reset Architecture (synchronisers, trees, sequencers) and Reset Domain Crossing (isolation patterns and quiescence). Link back to those for construction; this section covers what signoff checks and how to debug.
Reset Sequencing: correct synchronisers align each release to its own clock but do not order the releases, so a producer can send before its consumer is ready.